update clock constraints for SATA1 and use sys_clk of 200MHz

- data seems stable (mila capture) except when receive the ALIGN primtive from the device, we should maybe disable alignment on the HOST when link is ready...

diff --git a/lib/sata/phy/k7sataphy/crg.py b/lib/sata/phy/k7sataphy/crg.py
index 40d607f2a284259d726affdaa3d85e064e66509e..2166fa7742718b8eb3ccef1e2c483f6fd9401bc2 100644 (file)
--- a/lib/sata/phy/k7sataphy/crg.py
+++ b/lib/sata/phy/k7sataphy/crg.py
@@ -80,10 +80,9 @@ class K7SATAPHYCRG(Module):
                # (SATA3) sata_rx recovered clk @ 300MHz from GTX RXOUTCLK
                # (SATA2) sata_rx recovered clk @ 150MHz from GTX RXOUTCLK
                # (SATA1) sata_rx recovered clk @ 150MHz from GTX RXOUTCLK
-               #self.specials += [
-               #       Instance("BUFG", i_I=gtx.rxoutclk, o_O=self.cd_sata_rx.clk),
-               #]
-               self.comb += self.cd_sata_tx.clk.eq(self.cd_sata_tx.clk)
+               self.specials += [
+                       Instance("BUFG", i_I=gtx.rxoutclk, o_O=self.cd_sata_rx.clk),
+               ]
                self.comb += [
                        gtx.rxusrclk.eq(self.cd_sata_rx.clk),
                        gtx.rxusrclk2.eq(self.cd_sata_rx.clk)

diff --git a/platforms/kc705.py b/platforms/kc705.py
index a743d24b3977f29c82cbd656d39b23439f7c5551..46ebe3673b1f1b2140a0e7ee835099f1ccdeb94d 100644 (file)
--- a/platforms/kc705.py
+++ b/platforms/kc705.py
@@ -128,9 +128,17 @@ def Platform(*args, toolchain="vivado", programmer="xc3sprog", **kwargs):
                        except ConstraintError:
                                pass
                        self.add_platform_command("""
-create_clock -name sys_clk -period 6 [get_nets sys_clk]
+create_clock -name sys_clk -period 5 [get_nets sys_clk]
 create_clock -name sata_rx_clk -period 3.33 [get_nets sata_rx_clk]
 create_clock -name sata_tx_clk -period 3.33 [get_nets sata_tx_clk]
+
+set_false_path -from [get_clocks sys_clk] -to [get_clocks sata_rx_clk]
+set_false_path -from [get_clocks sys_clk] -to [get_clocks sata_tx_clk]
+set_false_path -from [get_clocks sata_rx_clk] -to [get_clocks sys_clk]
+set_false_path -from [get_clocks sata_tx_clk] -to [get_clocks sys_clk]
+
+set_property CFGBVS VCCO [current_design]
+set_property CONFIG_VOLTAGE 2.5 [current_design]
 """)
 
        return RealPlatform(*args, **kwargs)

diff --git a/targets/test.py b/targets/test.py
index bc3e90543893cd9749e73ba9a21b174b3ab9e010..097222f5ff626fd780fbd30c14f9ead9bf57b07f 100644 (file)
--- a/targets/test.py
+++ b/targets/test.py
@@ -36,7 +36,7 @@ class _CRG(Module):
                                i_CLKIN1=clk200_se, i_CLKFBIN=pll_fb, o_CLKFBOUT=pll_fb,
 
                                # 100MHz
-                               p_CLKOUT0_DIVIDE=10, p_CLKOUT0_PHASE=0.0, o_CLKOUT0=pll_sys,
+                               p_CLKOUT0_DIVIDE=5, p_CLKOUT0_PHASE=0.0, o_CLKOUT0=pll_sys,
 
                                p_CLKOUT1_DIVIDE=2, p_CLKOUT1_PHASE=0.0, #o_CLKOUT1=,
 
@@ -107,7 +107,7 @@ class SimDesign(UART2WB):
        default_platform = "kc705"
 
        def __init__(self, platform, export_mila=False):
-               clk_freq = 100*1000000
+               clk_freq = 200*1000000
                UART2WB.__init__(self, platform, clk_freq)
                self.submodules.crg = _CRG(platform)
 
@@ -169,6 +169,8 @@ class VeryBasicPHYStim(Module, AutoCSR):
                                If(self.cont_remover.source.stb & (self.cont_remover.source.charisk == 0b0001),
                                        self._rx_primitive.status.eq(self.cont_remover.source.data)
                                )
+                       ).Else(
+                               self.cont_inserter.sink.data.eq(primitives["SYNC"]),
                        )
                ]
 
@@ -181,7 +183,7 @@ class TestDesign(UART2WB, AutoCSR):
        csr_map.update(UART2WB.csr_map)
 
        def __init__(self, platform, mila=True, export_mila=False):
-               clk_freq = 100*1000000
+               clk_freq = 200*1000000
                UART2WB.__init__(self, platform, clk_freq)
                self.submodules.crg = _CRG(platform)
 

diff --git a/test/test_stim.py b/test/test_stim.py
index a379869f66264aa3b95686d11bdb505f03914a1a..b69665171bf23784c4ecc7918096b008e1b9e865 100644 (file)
--- a/test/test_stim.py
+++ b/test/test_stim.py
@@ -33,7 +33,7 @@ for i in range(16):
        rx = regs.stim_rx_primitive.read()
        print("rx: %08x %s" %(rx, decode_primitive(rx)))
        time.sleep(0.1)
-regs.stim_tx_primitive.write(primitives["R_RDY"])
+#regs.stim_tx_primitive.write(primitives["R_RDY"])
 for i in range(16):
        rx = regs.stim_rx_primitive.read()
        print("rx: %08x %s" %(rx, decode_primitive(rx)))