arch-power: Add fields for VA form instructions

This introduces the extended opcode field for VA form
instructions and the RC field that specifes a GPR to
be used as a register operand.

Change-Id: Ibc63b7392cb552613c755463fb34f2ee2362b2b6
Signed-off-by: Sandipan Das <sandipan@linux.ibm.com>

diff --git a/src/arch/power/isa/bitfields.isa b/src/arch/power/isa/bitfields.isa
index 84a3a2cfe4a5229120b0b8645598f4753d74003a..8783081e2637a74d24255cf4bf3c57d2b4a11ca4 100644 (file)
--- a/src/arch/power/isa/bitfields.isa
+++ b/src/arch/power/isa/bitfields.isa
@@ -38,6 +38,7 @@ def bitfield PO            <31:26>;
 def bitfield A_XO          <5:1>;
 def bitfield DS_XO         <1:0>;
 def bitfield DX_XO         <5:1>;
+def bitfield VA_XO         <5:0>;
 def bitfield X_XO          <10:1>;
 def bitfield XFL_XO        <10:1>;
 def bitfield XFX_XO        <10:1>;
@@ -47,6 +48,7 @@ def bitfield XO_XO         <9:1>;
 // Register fields
 def bitfield RA            <20:16>;
 def bitfield RB            <15:11>;
+def bitfield RC            <10:6>;
 def bitfield RS            <25:21>;
 def bitfield RT            <25:21>;
 def bitfield FRA           <20:16>;

diff --git a/src/arch/power/isa/operands.isa b/src/arch/power/isa/operands.isa
index 017469a01e8fb11b4594312b5f9e8a102970f54c..bdd59484367ec55e325fe3a13965636202ddf809 100644 (file)
--- a/src/arch/power/isa/operands.isa
+++ b/src/arch/power/isa/operands.isa
@@ -44,7 +44,8 @@ def operands {{
     'Rs': ('IntReg', 'ud', 'RS', 'IsInteger', 1),
     'Ra': ('IntReg', 'ud', 'RA', 'IsInteger', 2),
     'Rb': ('IntReg', 'ud', 'RB', 'IsInteger', 3),
-    'Rt': ('IntReg', 'ud', 'RT', 'IsInteger', 4),
+    'Rc': ('IntReg', 'ud', 'RC', 'IsInteger', 4),
+    'Rt': ('IntReg', 'ud', 'RT', 'IsInteger', 5),
 
     # General Purpose Floating Point Reg Operands
     'Fa': ('FloatReg', 'df', 'FRA', 'IsFloating', 1),