add image links to ECP5 page

diff --git a/HDL_workflow/ECP5_FPGA.mdwn b/HDL_workflow/ECP5_FPGA.mdwn
index 5ff231436a67d59d523e9c9f1785b89457b1327b..b754d902a4bc20cf381ad42a22df85d9016f1ff0 100644 (file)
--- a/HDL_workflow/ECP5_FPGA.mdwn
+++ b/HDL_workflow/ECP5_FPGA.mdwn
@@ -163,3 +163,10 @@ Luke do the labels of PCLK[C|T]0_[0|1] and GR_PCLK0_[0|1] have any significance?
 
 Additionally, does the note in the schematic about needing to swap EVEN and ODD pin numbers if using MALE VERTICAL header instead of FEMALE 90° ANGLED header apply to us?
 
+# VERSA ECP5 Connections
+
+[[!img 2020-11-03_13-22.png size="900x" ]] 
+
+[[!img 2020-11-03_13-25.png size="900x" ]] 
+
+[[!img versa_ecp5_x3_connector.jpg size="900x" ]]