liteXXX cores: remove redefinition of get_csr_csv

diff --git a/misoclib/com/liteeth/example_designs/make.py b/misoclib/com/liteeth/example_designs/make.py
index 706944849a37436f4856481da22aa9428980feea..44e2328476bee737cb8aea4bc225c15456e15021 100644 (file)
--- a/misoclib/com/liteeth/example_designs/make.py
+++ b/misoclib/com/liteeth/example_designs/make.py
@@ -11,18 +11,9 @@ from mibuild import tools
 from mibuild.xilinx.common import *
 
 sys.path.append("../../../../") # Temporary
+from misoclib.soc import cpuif
 from misoclib.com.liteeth.common import *
 
-def get_csr_csv(regions):
-       r = ""
-       for name, origin, busword, obj in regions:
-               if not isinstance(obj, Memory):
-                       for csr in obj:
-                               nr = (csr.size + busword - 1)//busword
-                               r += "{}_{},0x{:08x},{},{}\n".format(name, csr.name, origin, nr, "ro" if isinstance(csr, CSRStatus) else "rw")
-                               origin += 4*nr
-       return r
-
 def _import(default, name):
        return importlib.import_module(default + "." + name)
 
@@ -128,7 +119,7 @@ System Clk: {} MHz
                subprocess.call(["rm", "-rf", "build/*"])
 
        if actions["build-csr-csv"]:
-               csr_csv = get_csr_csv(soc.cpu_csr_regions)
+               csr_csv = cpuif.get_csr_csv(soc.cpu_csr_regions)
                write_to_file(args.csr_csv, csr_csv)
 
        if actions["build-bitstream"]:

diff --git a/misoclib/mem/litesata/example_designs/make.py b/misoclib/mem/litesata/example_designs/make.py
index 820b872ffdf01a68fd293a77b4bb26506946225b..ad8ff7df0e62aba55caf4eb386c10a1ea53e6851 100644 (file)
--- a/misoclib/mem/litesata/example_designs/make.py
+++ b/misoclib/mem/litesata/example_designs/make.py
@@ -11,18 +11,9 @@ from mibuild import tools
 from mibuild.xilinx.common import *
 
 sys.path.append("../../../../") # Temporary
+from misoclib.soc import cpuif
 from misoclib.mem.litesata.common import *
 
-def get_csr_csv(regions):
-       r = ""
-       for name, origin, busword, obj in regions:
-               if not isinstance(obj, Memory):
-                       for csr in obj:
-                               nr = (csr.size + busword - 1)//busword
-                               r += "{}_{},0x{:08x},{},{}\n".format(name, csr.name, origin, nr, "ro" if isinstance(csr, CSRStatus) else "rw")
-                               origin += 4*nr
-       return r
-
 def _import(default, name):
        return importlib.import_module(default + "." + name)
 
@@ -134,7 +125,7 @@ BIST: {}
                subprocess.call(["rm", "-rf", "build/*"])
 
        if actions["build-csr-csv"]:
-               csr_csv = get_csr_csv(soc.cpu_csr_regions)
+               csr_csv = cpuif.get_csr_csv(soc.cpu_csr_regions)
                write_to_file(args.csr_csv, csr_csv)
 
        if actions["build-core"]:

diff --git a/misoclib/tools/litescope/example_designs/make.py b/misoclib/tools/litescope/example_designs/make.py
index e73294f55e545da9a868c04f6618c71a2cc44c3b..64e2c499a28cc262d94ac15232959201443a3a98 100644 (file)
--- a/misoclib/tools/litescope/example_designs/make.py
+++ b/misoclib/tools/litescope/example_designs/make.py
@@ -11,18 +11,9 @@ from mibuild import tools
 from mibuild.xilinx.common import *
 
 sys.path.append("../../../../") # Temporary
+from misoclib.soc import cpuif
 from misoclib.tools.litescope.common import *
 
-def get_csr_csv(regions):
-       r = ""
-       for name, origin, busword, obj in regions:
-               if not isinstance(obj, Memory):
-                       for csr in obj:
-                               nr = (csr.size + busword - 1)//busword
-                               r += "{}_{},0x{:08x},{},{}\n".format(name, csr.name, origin, nr, "ro" if isinstance(csr, CSRStatus) else "rw")
-                               origin += 4*nr
-       return r
-
 def _import(default, name):
        return importlib.import_module(default + "." + name)
 
@@ -137,7 +128,7 @@ RLE: {}
                subprocess.call(["rm", "-rf", "build/*"])
 
        if actions["build-csr-csv"]:
-               csr_csv = get_csr_csv(soc.cpu_csr_regions)
+               csr_csv = cpuif.get_csr_csv(soc.cpu_csr_regions)
                write_to_file(args.csr_csv, csr_csv)
 
        if actions["build-bitstream"]: