* doc/invoke.texi: Document AMD bdver1 and btver1.

From-SVN: r181417

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 7bb2b600804a7ad7a42c899cc19a470f136201d9..218681a1edc98e0dffc5659d936193d367e47e72 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,7 @@
+2011-11-16  Venkataramanan Kumar  <venkataramanan.kumar@amd.com>
+
+       * doc/invoke.texi: Document AMD bdver1 and btver1.
+
 2011-11-16  Richard Earnshaw  <rearnsha@arm.com>
            Bernd Schmidt <bernds@coudesourcery.com>
            Sebastian Huber <sebastian.huber@embedded-brains.de>

diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi
index 1fc44372e322ecc447e8be99b6f4706ba93a44ea..e58ed1b4ac53cf7d8c1fdebaeb0834252bb80899 100644 (file)
--- a/gcc/doc/invoke.texi
+++ b/gcc/doc/invoke.texi
@@ -12803,6 +12803,15 @@ Improved versions of k8, opteron and athlon64 with SSE3 instruction set support.
 AMD Family 10h core based CPUs with x86-64 instruction set support.  (This
 supersets MMX, SSE, SSE2, SSE3, SSE4A, 3DNow!, enhanced 3DNow!, ABM and 64-bit
 instruction set extensions.)
+@item bdver1
+AMD Family 15h core based CPUs with x86-64 instruction set support.  (This
+supersets FMA4, AVX, XOP, LWP, AES, PCL_MUL, CX16, MMX, SSE, SSE2, SSE3, SSE4A,
+SSSE3, SSE4.1, SSE4.2, 3DNow!, enhanced 3DNow!, ABM and 64-bit
+instruction set extensions.)
+@item btver1
+AMD Family 14h core based CPUs with x86-64 instruction set support.  (This
+supersets MMX, SSE, SSE2, SSE3, SSSE3, SSE4A, CX16, ABM and 64-bit
+instruction set extensions.)
 @item winchip-c6
 IDT Winchip C6 CPU, dealt in same way as i486 with additional MMX instruction
 set support.