build.plat: TemplatedPlatform.iter_extra_files→Platform.iter_files.

This function was added in commit 20553b14 in the wrong place, with
the wrong name, and without tests. Fix all that.

diff --git a/nmigen/build/plat.py b/nmigen/build/plat.py
index 31c9704ccb8d346e8bbde98f2fe77822793d8aa0..750a4779f904e5d936c38f8e85b1e45456614be2 100644 (file)
--- a/nmigen/build/plat.py
+++ b/nmigen/build/plat.py
@@ -63,6 +63,11 @@ class Platform(ResourceManager, metaclass=ABCMeta):
         else:
             self.extra_files[filename] = content
 
+    def iter_files(self, *suffixes):
+        for filename in self.extra_files:
+            if filename.endswith(suffixes):
+                yield filename
+
     @property
     def _toolchain_env_var(self):
         return f"NMIGEN_ENV_{self.toolchain}"
@@ -437,6 +442,3 @@ class TemplatedPlatform(Platform):
         for filename, content in self.extra_files.items():
             plan.add_file(filename, content)
         return plan
-
-    def iter_extra_files(self, *endswith):
-        return (f for f in self.extra_files if f.endswith(endswith))

diff --git a/nmigen/vendor/intel.py b/nmigen/vendor/intel.py
index 8393deab9d1c9ea3d37f87f3569267b903a54ef8..dc1f1bc7a2e8d55a411f63246a0e42e9bc5e0956 100644 (file)
--- a/nmigen/vendor/intel.py
+++ b/nmigen/vendor/intel.py
@@ -82,13 +82,13 @@ class IntelPlatform(TemplatedPlatform):
                 set_global_assignment -name NUM_PARALLEL_PROCESSORS {{get_override("nproc")}}
             {% endif %}
 
-            {% for file in platform.iter_extra_files(".v") -%}
+            {% for file in platform.iter_files(".v") -%}
                 set_global_assignment -name VERILOG_FILE {{file|tcl_quote}}
             {% endfor %}
-            {% for file in platform.iter_extra_files(".sv") -%}
+            {% for file in platform.iter_files(".sv") -%}
                 set_global_assignment -name SYSTEMVERILOG_FILE {{file|tcl_quote}}
             {% endfor %}
-            {% for file in platform.iter_extra_files(".vhd", ".vhdl") -%}
+            {% for file in platform.iter_files(".vhd", ".vhdl") -%}
                 set_global_assignment -name VHDL_FILE {{file|tcl_quote}}
             {% endfor %}
             set_global_assignment -name VERILOG_FILE {{name}}.v

diff --git a/nmigen/vendor/lattice_ecp5.py b/nmigen/vendor/lattice_ecp5.py
index 2a68dadc9585770a7ee32daebce7d886287182ea..2775c91324b6f72077c5953d717dbda54d681086 100644 (file)
--- a/nmigen/vendor/lattice_ecp5.py
+++ b/nmigen/vendor/lattice_ecp5.py
@@ -112,13 +112,13 @@ class LatticeECP5Platform(TemplatedPlatform):
         """,
         "{{name}}.ys": r"""
             # {{autogenerated}}
-            {% for file in platform.iter_extra_files(".v") -%}
+            {% for file in platform.iter_files(".v") -%}
                 read_verilog {{get_override("read_verilog_opts")|options}} {{file}}
             {% endfor %}
-            {% for file in platform.iter_extra_files(".sv") -%}
+            {% for file in platform.iter_files(".sv") -%}
                 read_verilog -sv {{get_override("read_verilog_opts")|options}} {{file}}
             {% endfor %}
-            {% for file in platform.iter_extra_files(".il") -%}
+            {% for file in platform.iter_files(".il") -%}
                 read_ilang {{file}}
             {% endfor %}
             read_ilang {{name}}.il
@@ -210,7 +210,7 @@ class LatticeECP5Platform(TemplatedPlatform):
                 -dev {{platform.device}}-{{platform.speed}}{{platform.package}}{{platform.grade}} \
                 -lpf {{name}}.lpf \
                 -synthesis synplify
-            {% for file in platform.iter_extra_files(".v", ".sv", ".vhd", ".vhdl") -%}
+            {% for file in platform.iter_files(".v", ".sv", ".vhd", ".vhdl") -%}
                 prj_src add {{file|tcl_escape}}
             {% endfor %}
             prj_src add {{name}}.v

diff --git a/nmigen/vendor/lattice_ice40.py b/nmigen/vendor/lattice_ice40.py
index 4e6b2820fe1b8e890127796095e684fb06dc9d14..c9c35b353096b509b743ebd5f807cc9533dd105c 100644 (file)
--- a/nmigen/vendor/lattice_ice40.py
+++ b/nmigen/vendor/lattice_ice40.py
@@ -114,13 +114,13 @@ class LatticeICE40Platform(TemplatedPlatform):
         """,
         "{{name}}.ys": r"""
             # {{autogenerated}}
-            {% for file in platform.iter_extra_files(".v") -%}
+            {% for file in platform.iter_files(".v") -%}
                 read_verilog {{get_override("read_verilog_opts")|options}} {{file}}
             {% endfor %}
-            {% for file in platform.iter_extra_files(".sv") -%}
+            {% for file in platform.iter_files(".sv") -%}
                 read_verilog -sv {{get_override("read_verilog_opts")|options}} {{file}}
             {% endfor %}
-            {% for file in platform.iter_extra_files(".il") -%}
+            {% for file in platform.iter_files(".il") -%}
                 read_ilang {{file}}
             {% endfor %}
             read_ilang {{name}}.il
@@ -212,7 +212,7 @@ class LatticeICE40Platform(TemplatedPlatform):
             -d {{platform.device}}
             -t {{platform.package}}
             {{get_override("lse_opts")|options|default("# (lse_opts placeholder)")}}
-            {% for file in platform.iter_extra_files(".v") -%}
+            {% for file in platform.iter_files(".v") -%}
                 -ver {{file}}
             {% endfor %}
             -ver {{name}}.v
@@ -223,7 +223,7 @@ class LatticeICE40Platform(TemplatedPlatform):
         """,
         "{{name}}_syn.prj": r"""
             # {{autogenerated}}
-            {% for file in platform.iter_extra_files(".v", ".sv", ".vhd", ".vhdl") -%}
+            {% for file in platform.iter_files(".v", ".sv", ".vhd", ".vhdl") -%}
                 add_file -verilog {{file|tcl_escape}}
             {% endfor %}
             add_file -verilog {{name}}.v

diff --git a/nmigen/vendor/lattice_machxo_2_3l.py b/nmigen/vendor/lattice_machxo_2_3l.py
index 08c6008f44fe266310e62eec4b29a2be565190bf..64aa193482ac8628da50c04b3d2b9e86d94b9e36 100644 (file)
--- a/nmigen/vendor/lattice_machxo_2_3l.py
+++ b/nmigen/vendor/lattice_machxo_2_3l.py
@@ -74,7 +74,7 @@ class LatticeMachXO2Or3LPlatform(TemplatedPlatform):
                 -dev {{platform.device}}-{{platform.speed}}{{platform.package}}{{platform.grade}} \
                 -lpf {{name}}.lpf \
                 -synthesis synplify
-            {% for file in platform.iter_extra_files(".v", ".sv", ".vhd", ".vhdl") -%}
+            {% for file in platform.iter_files(".v", ".sv", ".vhd", ".vhdl") -%}
                 prj_src add {{file|tcl_escape}}
             {% endfor %}
             prj_src add {{name}}.v

diff --git a/nmigen/vendor/quicklogic.py b/nmigen/vendor/quicklogic.py
index c8bd5cb267310be940f347c395dd7068fefa76bc..6e9c63cee4865d06f1ccdec722ee84b5f35d7238 100644 (file)
--- a/nmigen/vendor/quicklogic.py
+++ b/nmigen/vendor/quicklogic.py
@@ -82,7 +82,7 @@ class QuicklogicPlatform(TemplatedPlatform):
         r"""
         {{invoke_tool("symbiflow_synth")}}
             -t {{name}}
-            -v {% for file in platform.iter_extra_files(".v", ".sv", ".vhd", ".vhdl") -%} {{file}} {% endfor %} {{name}}.v
+            -v {% for file in platform.iter_files(".v", ".sv", ".vhd", ".vhdl") -%} {{file}} {% endfor %} {{name}}.v
             -d {{platform.device}}
             -p {{name}}.pcf
             -P {{platform.package}}

diff --git a/nmigen/vendor/xilinx_7series.py b/nmigen/vendor/xilinx_7series.py
index 9dd738c57f21c4cff1ea1cc8b5383cdf4c6f83e2..084d2ba521809139d143c8867a8bcde44197facd 100644 (file)
--- a/nmigen/vendor/xilinx_7series.py
+++ b/nmigen/vendor/xilinx_7series.py
@@ -99,12 +99,12 @@ class Xilinx7SeriesPlatform(TemplatedPlatform):
         "{{name}}.tcl": r"""
             # {{autogenerated}}
             create_project -force -name {{name}} -part {{platform._part}}
-            {% for file in platform.iter_extra_files(".v", ".sv", ".vhd", ".vhdl") -%}
+            {% for file in platform.iter_files(".v", ".sv", ".vhd", ".vhdl") -%}
                 add_files {{file|tcl_escape}}
             {% endfor %}
             add_files {{name}}.v
             read_xdc {{name}}.xdc
-            {% for file in platform.iter_extra_files(".xdc") -%}
+            {% for file in platform.iter_files(".xdc") -%}
                 read_xdc {{file|tcl_escape}}
             {% endfor %}
             {{get_override("script_after_read")|default("# (script_after_read placeholder)")}}
@@ -229,7 +229,7 @@ class Xilinx7SeriesPlatform(TemplatedPlatform):
         r"""
         {{invoke_tool("synth")}}
             -t {{name}}
-            -v {% for file in platform.iter_extra_files(".v", ".sv", ".vhd", ".vhdl") -%} {{file}} {% endfor %} {{name}}.v
+            -v {% for file in platform.iter_files(".v", ".sv", ".vhd", ".vhdl") -%} {{file}} {% endfor %} {{name}}.v
             -p {{platform._symbiflow_part_map.get(platform._part, platform._part)}}
             -x {{name}}.xdc
         """,

diff --git a/nmigen/vendor/xilinx_spartan_3_6.py b/nmigen/vendor/xilinx_spartan_3_6.py
index 9b10733b2653a51f30d41a443da7b8400e348421..527d089cf6b36d4054e4e6fc77bc8ea2ae91ea33 100644 (file)
--- a/nmigen/vendor/xilinx_spartan_3_6.py
+++ b/nmigen/vendor/xilinx_spartan_3_6.py
@@ -102,10 +102,10 @@ class XilinxSpartan3Or6Platform(TemplatedPlatform):
         """,
         "{{name}}.prj": r"""
             # {{autogenerated}}
-            {% for file in platform.iter_extra_files(".vhd", ".vhdl") -%}
+            {% for file in platform.iter_files(".vhd", ".vhdl") -%}
                 vhdl work {{file}}
             {% endfor %}
-            {% for file in platform.iter_extra_files(".v") -%}
+            {% for file in platform.iter_files(".v") -%}
                 verilog work {{file}}
             {% endfor %}
             verilog work {{name}}.v

diff --git a/nmigen/vendor/xilinx_ultrascale.py b/nmigen/vendor/xilinx_ultrascale.py
index 0969ccba455a6f87362e5e539f6d6936258b9e85..bc28ac28a5c0d3c06ec39571e17155aa304df860 100644 (file)
--- a/nmigen/vendor/xilinx_ultrascale.py
+++ b/nmigen/vendor/xilinx_ultrascale.py
@@ -73,12 +73,12 @@ class XilinxUltraScalePlatform(TemplatedPlatform):
         "{{name}}.tcl": r"""
             # {{autogenerated}}
             create_project -force -name {{name}} -part {{platform.device}}-{{platform.package}}-{{platform.speed}}
-            {% for file in platform.iter_extra_files(".v", ".sv", ".vhd", ".vhdl") -%}
+            {% for file in platform.iter_files(".v", ".sv", ".vhd", ".vhdl") -%}
                 add_files {{file|tcl_escape}}
             {% endfor %}
             add_files {{name}}.v
             read_xdc {{name}}.xdc
-            {% for file in platform.iter_extra_files(".xdc") -%}
+            {% for file in platform.iter_files(".xdc") -%}
                 read_xdc {{file|tcl_escape}}
             {% endfor %}
             {{get_override("script_after_read")|default("# (script_after_read placeholder)")}}

diff --git a/tests/test_build_plat.py b/tests/test_build_plat.py
index 31dc5c9311b7aedcb464f12bc0cde86493c9d275..76a5331f3ad1e6af5acc7f1e99ce4a2218edaa2b 100644 (file)
--- a/tests/test_build_plat.py
+++ b/tests/test_build_plat.py
@@ -51,3 +51,14 @@ class PlatformTestCase(FHDLTestCase):
         with self.assertRaisesRegex(ValueError,
                 r"^File 'foo' already exists$"):
             self.platform.add_file("foo", "bar")
+
+    def test_iter_files(self):
+        self.platform.add_file("foo.v", "")
+        self.platform.add_file("bar.v", "")
+        self.platform.add_file("baz.vhd", "")
+        self.assertEqual(list(self.platform.iter_files(".v")),
+                         ["foo.v", "bar.v"])
+        self.assertEqual(list(self.platform.iter_files(".vhd")),
+                         ["baz.vhd"])
+        self.assertEqual(list(self.platform.iter_files(".v", ".vhd")),
+                         ["foo.v", "bar.v", "baz.vhd"])