Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
o <= i[4*W+:W];
endmodule
-module cliffordwolf_nonexclusive_select (
+module clairexen_nonexclusive_select (
input wire x, y, z,
input wire a, b, c, d,
output reg o
end
endmodule
-module cliffordwolf_freduce (
+module clairexen_freduce (
input wire [1:0] s,
input wire a, b, c, d,
output reg [3:0] o
sat -verify -prove-asserts -show-ports miter
design -load read
-hierarchy -top cliffordwolf_nonexclusive_select
+hierarchy -top clairexen_nonexclusive_select
prep
design -save gold
muxpack
sat -verify -prove-asserts -show-ports miter
#design -load read
-#hierarchy -top cliffordwolf_freduce
+#hierarchy -top clairexen_freduce
#prep
#design -save gold
#proc; opt; freduce; opt