Jan Hubicka <hubicka@freesoft.cz>

Jan Hubicka <hubicka@freesoft.cz>
        * i386.md: Do not output mov %0,reg on AMD K6.

From-SVN: r26406

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index ee6ed839e91f24fef5130e2e8522040f9a672bd6..9cdc3f422e0009c4baafd881ae2ef134361195de 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,7 @@
+Tue Apr 13 14:14:06 1999  Jan Hubicka <hubicka@freesoft.cz>
+
+       * i386.md: Do not output mov %0,reg on AMD K6.
+
 Tue Apr 13 12:14:07 1999  Dave Brolley  <brolley@cygnus.com>
 
        * cppinit.c (cpp_start_read): Fix buffer overwrite.

diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md
index 8eade3ebb58ba498804bd3cba5c12bcacee0f968..7e143ac197cbc240b766938b5e62d333e2a71b29 100644 (file)
--- a/gcc/config/i386/i386.md
+++ b/gcc/config/i386/i386.md
@@ -983,8 +983,13 @@
   "*
 {
   rtx link;
-  if ((ix86_cpu != PROCESSOR_K6 || optimize_size)
-      && operands[1] == const0_rtx && REG_P (operands[0]))
+
+  /* Use of xor was disabled for AMD K6 as recommended by the Optimization
+     Manual.  My test shows, that this generally hurts the performance, because
+     mov is longer and takes longer to decode and decoding is the main
+     bottleneck of K6 when executing GCC code.  */
+
+  if (operands[1] == const0_rtx && REG_P (operands[0]))
     return AS2 (xor%L0,%0,%0);
 
   if (operands[1] == const1_rtx
@@ -1111,8 +1116,13 @@
   "*
 {
   rtx link;
-  if ((ix86_cpu != PROCESSOR_K6 || optimize_size)
-      && operands[1] == const0_rtx && REG_P (operands[0]))
+
+  /* Use of xor was disabled for AMD K6 as recommended by the Optimization
+     Manual.  My test shows, that this generally hurts the performance, because
+     mov is longer and takes longer to decode and decoding is the main
+     bottleneck of K6 when executing GCC code.  */
+
+  if (operands[1] == const0_rtx && REG_P (operands[0]))
     return AS2 (xor%W0,%0,%0);
 
   if (operands[1] == const1_rtx