else if (GE && g) Q = D;
endmodule
+// LUTRAM.
+
+// Single port.
+
+module RAM16X1S (
+ output O,
+ input A0, A1, A2, A3,
+ input D,
+ (* clkbuf_sink *)
+ (* invertible_pin = "IS_WCLK_INVERTED" *)
+ input WCLK,
+ input WE
+);
+ parameter [15:0] INIT = 16'h0000;
+ parameter [0:0] IS_WCLK_INVERTED = 1'b0;
+ wire [3:0] a = {A3, A2, A1, A0};
+ reg [15:0] mem = INIT;
+ assign O = mem[a];
+ wire clk = WCLK ^ IS_WCLK_INVERTED;
+ always @(posedge clk) if (WE) mem[a] <= D;
+endmodule
+
+module RAM16X1S_1 (
+ output O,
+ input A0, A1, A2, A3,
+ input D,
+ (* clkbuf_sink *)
+ (* invertible_pin = "IS_WCLK_INVERTED" *)
+ input WCLK,
+ input WE
+);
+ parameter [15:0] INIT = 16'h0000;
+ parameter [0:0] IS_WCLK_INVERTED = 1'b0;
+ wire [3:0] a = {A3, A2, A1, A0};
+ reg [15:0] mem = INIT;
+ assign O = mem[a];
+ wire clk = WCLK ^ IS_WCLK_INVERTED;
+ always @(negedge clk) if (WE) mem[a] <= D;
+endmodule
+
+module RAM32X1S (
+ output O,
+ input A0, A1, A2, A3, A4,
+ input D,
+ (* clkbuf_sink *)
+ (* invertible_pin = "IS_WCLK_INVERTED" *)
+ input WCLK,
+ input WE
+);
+ parameter [31:0] INIT = 32'h00000000;
+ parameter [0:0] IS_WCLK_INVERTED = 1'b0;
+ wire [4:0] a = {A4, A3, A2, A1, A0};
+ reg [31:0] mem = INIT;
+ assign O = mem[a];
+ wire clk = WCLK ^ IS_WCLK_INVERTED;
+ always @(posedge clk) if (WE) mem[a] <= D;
+endmodule
+
+module RAM32X1S_1 (
+ output O,
+ input A0, A1, A2, A3, A4,
+ input D,
+ (* clkbuf_sink *)
+ (* invertible_pin = "IS_WCLK_INVERTED" *)
+ input WCLK,
+ input WE
+);
+ parameter [31:0] INIT = 32'h00000000;
+ parameter [0:0] IS_WCLK_INVERTED = 1'b0;
+ wire [4:0] a = {A4, A3, A2, A1, A0};
+ reg [31:0] mem = INIT;
+ assign O = mem[a];
+ wire clk = WCLK ^ IS_WCLK_INVERTED;
+ always @(negedge clk) if (WE) mem[a] <= D;
+endmodule
+
+module RAM64X1S (
+ output O,
+ input A0, A1, A2, A3, A4, A5,
+ input D,
+ (* clkbuf_sink *)
+ (* invertible_pin = "IS_WCLK_INVERTED" *)
+ input WCLK,
+ input WE
+);
+ parameter [63:0] INIT = 64'h0000000000000000;
+ parameter [0:0] IS_WCLK_INVERTED = 1'b0;
+ wire [5:0] a = {A5, A4, A3, A2, A1, A0};
+ reg [63:0] mem = INIT;
+ assign O = mem[a];
+ wire clk = WCLK ^ IS_WCLK_INVERTED;
+ always @(posedge clk) if (WE) mem[a] <= D;
+endmodule
+
+module RAM64X1S_1 (
+ output O,
+ input A0, A1, A2, A3, A4, A5,
+ input D,
+ (* clkbuf_sink *)
+ (* invertible_pin = "IS_WCLK_INVERTED" *)
+ input WCLK,
+ input WE
+);
+ parameter [63:0] INIT = 64'h0000000000000000;
+ parameter [0:0] IS_WCLK_INVERTED = 1'b0;
+ wire [5:0] a = {A5, A4, A3, A2, A1, A0};
+ reg [63:0] mem = INIT;
+ assign O = mem[a];
+ wire clk = WCLK ^ IS_WCLK_INVERTED;
+ always @(negedge clk) if (WE) mem[a] <= D;
+endmodule
+
+module RAM128X1S (
+ output O,
+ input A0, A1, A2, A3, A4, A5, A6,
+ input D,
+ (* clkbuf_sink *)
+ (* invertible_pin = "IS_WCLK_INVERTED" *)
+ input WCLK,
+ input WE
+);
+ parameter [127:0] INIT = 128'h00000000000000000000000000000000;
+ parameter [0:0] IS_WCLK_INVERTED = 1'b0;
+ wire [6:0] a = {A6, A5, A4, A3, A2, A1, A0};
+ reg [127:0] mem = INIT;
+ assign O = mem[a];
+ wire clk = WCLK ^ IS_WCLK_INVERTED;
+ always @(posedge clk) if (WE) mem[a] <= D;
+endmodule
+
+module RAM128X1S_1 (
+ output O,
+ input A0, A1, A2, A3, A4, A5, A6,
+ input D,
+ (* clkbuf_sink *)
+ (* invertible_pin = "IS_WCLK_INVERTED" *)
+ input WCLK,
+ input WE
+);
+ parameter [127:0] INIT = 128'h00000000000000000000000000000000;
+ parameter [0:0] IS_WCLK_INVERTED = 1'b0;
+ wire [6:0] a = {A6, A5, A4, A3, A2, A1, A0};
+ reg [127:0] mem = INIT;
+ assign O = mem[a];
+ wire clk = WCLK ^ IS_WCLK_INVERTED;
+ always @(negedge clk) if (WE) mem[a] <= D;
+endmodule
+
+module RAM256X1S (
+ output O,
+ input [7:0] A,
+ input D,
+ (* clkbuf_sink *)
+ (* invertible_pin = "IS_WCLK_INVERTED" *)
+ input WCLK,
+ input WE
+);
+ parameter [255:0] INIT = 256'h0;
+ parameter [0:0] IS_WCLK_INVERTED = 1'b0;
+ reg [255:0] mem = INIT;
+ assign O = mem[A];
+ wire clk = WCLK ^ IS_WCLK_INVERTED;
+ always @(posedge clk) if (WE) mem[A] <= D;
+endmodule
+
+module RAM512X1S (
+ output O,
+ input [8:0] A,
+ input D,
+ (* clkbuf_sink *)
+ (* invertible_pin = "IS_WCLK_INVERTED" *)
+ input WCLK,
+ input WE
+);
+ parameter [511:0] INIT = 512'h0;
+ parameter [0:0] IS_WCLK_INVERTED = 1'b0;
+ reg [511:0] mem = INIT;
+ assign O = mem[A];
+ wire clk = WCLK ^ IS_WCLK_INVERTED;
+ always @(posedge clk) if (WE) mem[A] <= D;
+endmodule
+
+// Single port, wide.
+
+module RAM16X2S (
+ output O0, O1,
+ input A0, A1, A2, A3,
+ input D0, D1,
+ (* clkbuf_sink *)
+ (* invertible_pin = "IS_WCLK_INVERTED" *)
+ input WCLK,
+ input WE
+);
+ parameter [15:0] INIT_00 = 16'h0000;
+ parameter [15:0] INIT_01 = 16'h0000;
+ parameter [0:0] IS_WCLK_INVERTED = 1'b0;
+ wire [3:0] a = {A3, A2, A1, A0};
+ wire clk = WCLK ^ IS_WCLK_INVERTED;
+ reg [15:0] mem0 = INIT_00;
+ reg [15:0] mem1 = INIT_01;
+ assign O0 = mem0[a];
+ assign O1 = mem1[a];
+ always @(posedge clk)
+ if (WE) begin
+ mem0[a] <= D0;
+ mem1[a] <= D1;
+ end
+endmodule
+
+module RAM32X2S (
+ output O0, O1,
+ input A0, A1, A2, A3, A4,
+ input D0, D1,
+ (* clkbuf_sink *)
+ (* invertible_pin = "IS_WCLK_INVERTED" *)
+ input WCLK,
+ input WE
+);
+ parameter [31:0] INIT_00 = 32'h00000000;
+ parameter [31:0] INIT_01 = 32'h00000000;
+ parameter [0:0] IS_WCLK_INVERTED = 1'b0;
+ wire [4:0] a = {A4, A3, A2, A1, A0};
+ wire clk = WCLK ^ IS_WCLK_INVERTED;
+ reg [31:0] mem0 = INIT_00;
+ reg [31:0] mem1 = INIT_01;
+ assign O0 = mem0[a];
+ assign O1 = mem1[a];
+ always @(posedge clk)
+ if (WE) begin
+ mem0[a] <= D0;
+ mem1[a] <= D1;
+ end
+endmodule
+
+module RAM64X2S (
+ output O0, O1,
+ input A0, A1, A2, A3, A4, A5,
+ input D0, D1,
+ (* clkbuf_sink *)
+ (* invertible_pin = "IS_WCLK_INVERTED" *)
+ input WCLK,
+ input WE
+);
+ parameter [63:0] INIT_00 = 64'h0000000000000000;
+ parameter [63:0] INIT_01 = 64'h0000000000000000;
+ parameter [0:0] IS_WCLK_INVERTED = 1'b0;
+ wire [5:0] a = {A5, A3, A2, A1, A0};
+ wire clk = WCLK ^ IS_WCLK_INVERTED;
+ reg [63:0] mem0 = INIT_00;
+ reg [63:0] mem1 = INIT_01;
+ assign O0 = mem0[a];
+ assign O1 = mem1[a];
+ always @(posedge clk)
+ if (WE) begin
+ mem0[a] <= D0;
+ mem1[a] <= D1;
+ end
+endmodule
+
+module RAM16X4S (
+ output O0, O1, O2, O3,
+ input A0, A1, A2, A3,
+ input D0, D1, D2, D3,
+ (* clkbuf_sink *)
+ (* invertible_pin = "IS_WCLK_INVERTED" *)
+ input WCLK,
+ input WE
+);
+ parameter [15:0] INIT_00 = 16'h0000;
+ parameter [15:0] INIT_01 = 16'h0000;
+ parameter [15:0] INIT_02 = 16'h0000;
+ parameter [15:0] INIT_03 = 16'h0000;
+ parameter [0:0] IS_WCLK_INVERTED = 1'b0;
+ wire [3:0] a = {A3, A2, A1, A0};
+ wire clk = WCLK ^ IS_WCLK_INVERTED;
+ reg [15:0] mem0 = INIT_00;
+ reg [15:0] mem1 = INIT_01;
+ reg [15:0] mem2 = INIT_02;
+ reg [15:0] mem3 = INIT_03;
+ assign O0 = mem0[a];
+ assign O1 = mem1[a];
+ assign O2 = mem2[a];
+ assign O3 = mem3[a];
+ always @(posedge clk)
+ if (WE) begin
+ mem0[a] <= D0;
+ mem1[a] <= D1;
+ mem2[a] <= D2;
+ mem3[a] <= D3;
+ end
+endmodule
+
+module RAM32X4S (
+ output O0, O1, O2, O3,
+ input A0, A1, A2, A3, A4,
+ input D0, D1, D2, D3,
+ (* clkbuf_sink *)
+ (* invertible_pin = "IS_WCLK_INVERTED" *)
+ input WCLK,
+ input WE
+);
+ parameter [31:0] INIT_00 = 32'h00000000;
+ parameter [31:0] INIT_01 = 32'h00000000;
+ parameter [31:0] INIT_02 = 32'h00000000;
+ parameter [31:0] INIT_03 = 32'h00000000;
+ parameter [0:0] IS_WCLK_INVERTED = 1'b0;
+ wire [4:0] a = {A4, A3, A2, A1, A0};
+ wire clk = WCLK ^ IS_WCLK_INVERTED;
+ reg [31:0] mem0 = INIT_00;
+ reg [31:0] mem1 = INIT_01;
+ reg [31:0] mem2 = INIT_02;
+ reg [31:0] mem3 = INIT_03;
+ assign O0 = mem0[a];
+ assign O1 = mem1[a];
+ assign O2 = mem2[a];
+ assign O3 = mem3[a];
+ always @(posedge clk)
+ if (WE) begin
+ mem0[a] <= D0;
+ mem1[a] <= D1;
+ mem2[a] <= D2;
+ mem3[a] <= D3;
+ end
+endmodule
+
+module RAM16X8S (
+ output [7:0] O,
+ input A0, A1, A2, A3,
+ input [7:0] D,
+ (* clkbuf_sink *)
+ (* invertible_pin = "IS_WCLK_INVERTED" *)
+ input WCLK,
+ input WE
+);
+ parameter [15:0] INIT_00 = 16'h0000;
+ parameter [15:0] INIT_01 = 16'h0000;
+ parameter [15:0] INIT_02 = 16'h0000;
+ parameter [15:0] INIT_03 = 16'h0000;
+ parameter [15:0] INIT_04 = 16'h0000;
+ parameter [15:0] INIT_05 = 16'h0000;
+ parameter [15:0] INIT_06 = 16'h0000;
+ parameter [15:0] INIT_07 = 16'h0000;
+ parameter [0:0] IS_WCLK_INVERTED = 1'b0;
+ wire [3:0] a = {A3, A2, A1, A0};
+ wire clk = WCLK ^ IS_WCLK_INVERTED;
+ reg [15:0] mem0 = INIT_00;
+ reg [15:0] mem1 = INIT_01;
+ reg [15:0] mem2 = INIT_02;
+ reg [15:0] mem3 = INIT_03;
+ reg [15:0] mem4 = INIT_04;
+ reg [15:0] mem5 = INIT_05;
+ reg [15:0] mem6 = INIT_06;
+ reg [15:0] mem7 = INIT_07;
+ assign O[0] = mem0[a];
+ assign O[1] = mem1[a];
+ assign O[2] = mem2[a];
+ assign O[3] = mem3[a];
+ assign O[4] = mem4[a];
+ assign O[5] = mem5[a];
+ assign O[6] = mem6[a];
+ assign O[7] = mem7[a];
+ always @(posedge clk)
+ if (WE) begin
+ mem0[a] <= D[0];
+ mem1[a] <= D[1];
+ mem2[a] <= D[2];
+ mem3[a] <= D[3];
+ mem4[a] <= D[4];
+ mem5[a] <= D[5];
+ mem6[a] <= D[6];
+ mem7[a] <= D[7];
+ end
+endmodule
+
+module RAM32X8S (
+ output [7:0] O,
+ input A0, A1, A2, A3, A4,
+ input [7:0] D,
+ (* clkbuf_sink *)
+ (* invertible_pin = "IS_WCLK_INVERTED" *)
+ input WCLK,
+ input WE
+);
+ parameter [31:0] INIT_00 = 32'h00000000;
+ parameter [31:0] INIT_01 = 32'h00000000;
+ parameter [31:0] INIT_02 = 32'h00000000;
+ parameter [31:0] INIT_03 = 32'h00000000;
+ parameter [31:0] INIT_04 = 32'h00000000;
+ parameter [31:0] INIT_05 = 32'h00000000;
+ parameter [31:0] INIT_06 = 32'h00000000;
+ parameter [31:0] INIT_07 = 32'h00000000;
+ parameter [0:0] IS_WCLK_INVERTED = 1'b0;
+ wire [4:0] a = {A4, A3, A2, A1, A0};
+ wire clk = WCLK ^ IS_WCLK_INVERTED;
+ reg [31:0] mem0 = INIT_00;
+ reg [31:0] mem1 = INIT_01;
+ reg [31:0] mem2 = INIT_02;
+ reg [31:0] mem3 = INIT_03;
+ reg [31:0] mem4 = INIT_04;
+ reg [31:0] mem5 = INIT_05;
+ reg [31:0] mem6 = INIT_06;
+ reg [31:0] mem7 = INIT_07;
+ assign O[0] = mem0[a];
+ assign O[1] = mem1[a];
+ assign O[2] = mem2[a];
+ assign O[3] = mem3[a];
+ assign O[4] = mem4[a];
+ assign O[5] = mem5[a];
+ assign O[6] = mem6[a];
+ assign O[7] = mem7[a];
+ always @(posedge clk)
+ if (WE) begin
+ mem0[a] <= D[0];
+ mem1[a] <= D[1];
+ mem2[a] <= D[2];
+ mem3[a] <= D[3];
+ mem4[a] <= D[4];
+ mem5[a] <= D[5];
+ mem6[a] <= D[6];
+ mem7[a] <= D[7];
+ end
+endmodule
+
+// Dual port.
+
+module RAM16X1D (
+ output DPO, SPO,
+ input D,
+ (* clkbuf_sink *)
+ (* invertible_pin = "IS_WCLK_INVERTED" *)
+ input WCLK,
+ input WE,
+ input A0, A1, A2, A3,
+ input DPRA0, DPRA1, DPRA2, DPRA3
+);
+ parameter INIT = 16'h0;
+ parameter IS_WCLK_INVERTED = 1'b0;
+ wire [3:0] a = {A3, A2, A1, A0};
+ wire [3:0] dpra = {DPRA3, DPRA2, DPRA1, DPRA0};
+ reg [15:0] mem = INIT;
+ assign SPO = mem[a];
+ assign DPO = mem[dpra];
+ wire clk = WCLK ^ IS_WCLK_INVERTED;
+ always @(posedge clk) if (WE) mem[a] <= D;
+endmodule
+
+module RAM16X1D_1 (
+ output DPO, SPO,
+ input D,
+ (* clkbuf_sink *)
+ (* invertible_pin = "IS_WCLK_INVERTED" *)
+ input WCLK,
+ input WE,
+ input A0, A1, A2, A3,
+ input DPRA0, DPRA1, DPRA2, DPRA3
+);
+ parameter INIT = 16'h0;
+ parameter IS_WCLK_INVERTED = 1'b0;
+ wire [3:0] a = {A3, A2, A1, A0};
+ wire [3:0] dpra = {DPRA3, DPRA2, DPRA1, DPRA0};
+ reg [15:0] mem = INIT;
+ assign SPO = mem[a];
+ assign DPO = mem[dpra];
+ wire clk = WCLK ^ IS_WCLK_INVERTED;
+ always @(negedge clk) if (WE) mem[a] <= D;
+endmodule
+
module RAM32X1D (
// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L957
(* abc9_arrival=1153 *)
always @(posedge clk) if (WE) mem[a] <= D;
endmodule
+module RAM32X1D_1 (
+ // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L957
+ (* abc9_arrival=1153 *)
+ output DPO, SPO,
+ input D,
+ (* clkbuf_sink *)
+ (* invertible_pin = "IS_WCLK_INVERTED" *)
+ input WCLK,
+ input WE,
+ input A0, A1, A2, A3, A4,
+ input DPRA0, DPRA1, DPRA2, DPRA3, DPRA4
+);
+ parameter INIT = 32'h0;
+ parameter IS_WCLK_INVERTED = 1'b0;
+ wire [4:0] a = {A4, A3, A2, A1, A0};
+ wire [4:0] dpra = {DPRA4, DPRA3, DPRA2, DPRA1, DPRA0};
+ reg [31:0] mem = INIT;
+ assign SPO = mem[a];
+ assign DPO = mem[dpra];
+ wire clk = WCLK ^ IS_WCLK_INVERTED;
+ always @(negedge clk) if (WE) mem[a] <= D;
+endmodule
+
module RAM64X1D (
// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L957
(* abc9_arrival=1153 *)
always @(posedge clk) if (WE) mem[a] <= D;
endmodule
+module RAM64X1D_1 (
+ // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L957
+ (* abc9_arrival=1153 *)
+ output DPO, SPO,
+ input D,
+ (* clkbuf_sink *)
+ (* invertible_pin = "IS_WCLK_INVERTED" *)
+ input WCLK,
+ input WE,
+ input A0, A1, A2, A3, A4, A5,
+ input DPRA0, DPRA1, DPRA2, DPRA3, DPRA4, DPRA5
+);
+ parameter INIT = 64'h0;
+ parameter IS_WCLK_INVERTED = 1'b0;
+ wire [5:0] a = {A5, A4, A3, A2, A1, A0};
+ wire [5:0] dpra = {DPRA5, DPRA4, DPRA3, DPRA2, DPRA1, DPRA0};
+ reg [63:0] mem = INIT;
+ assign SPO = mem[a];
+ assign DPO = mem[dpra];
+ wire clk = WCLK ^ IS_WCLK_INVERTED;
+ always @(negedge clk) if (WE) mem[a] <= D;
+endmodule
+
module RAM128X1D (
// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L957
(* abc9_arrival=1153 *)
always @(posedge clk) if (WE) mem[A] <= D;
endmodule
+module RAM256X1D (
+ output DPO, SPO,
+ input D,
+ (* clkbuf_sink *)
+ (* invertible_pin = "IS_WCLK_INVERTED" *)
+ input WCLK,
+ input WE,
+ input [7:0] A, DPRA
+);
+ parameter INIT = 256'h0;
+ parameter IS_WCLK_INVERTED = 1'b0;
+ reg [255:0] mem = INIT;
+ assign SPO = mem[A];
+ assign DPO = mem[DPRA];
+ wire clk = WCLK ^ IS_WCLK_INVERTED;
+ always @(posedge clk) if (WE) mem[A] <= D;
+endmodule
+
+// Multi port.
+
+module RAM32M (
+ output [1:0] DOA,
+ output [1:0] DOB,
+ output [1:0] DOC,
+ output [1:0] DOD,
+ input [4:0] ADDRA,
+ input [4:0] ADDRB,
+ input [4:0] ADDRC,
+ input [4:0] ADDRD,
+ input [1:0] DIA,
+ input [1:0] DIB,
+ input [1:0] DIC,
+ input [1:0] DID,
+ (* clkbuf_sink *)
+ (* invertible_pin = "IS_WCLK_INVERTED" *)
+ input WCLK,
+ input WE
+);
+ parameter [63:0] INIT_A = 64'h0000000000000000;
+ parameter [63:0] INIT_B = 64'h0000000000000000;
+ parameter [63:0] INIT_C = 64'h0000000000000000;
+ parameter [63:0] INIT_D = 64'h0000000000000000;
+ parameter [0:0] IS_WCLK_INVERTED = 1'b0;
+ reg [63:0] mem_a = INIT_A;
+ reg [63:0] mem_b = INIT_B;
+ reg [63:0] mem_c = INIT_C;
+ reg [63:0] mem_d = INIT_D;
+ assign DOA = mem_a[2*ADDRA+:2];
+ assign DOB = mem_b[2*ADDRB+:2];
+ assign DOC = mem_c[2*ADDRC+:2];
+ assign DOD = mem_d[2*ADDRD+:2];
+ wire clk = WCLK ^ IS_WCLK_INVERTED;
+ always @(posedge clk)
+ if (WE) begin
+ mem_a[2*ADDRD+:2] <= DIA;
+ mem_b[2*ADDRD+:2] <= DIB;
+ mem_c[2*ADDRD+:2] <= DIC;
+ mem_d[2*ADDRD+:2] <= DID;
+ end
+endmodule
+
+module RAM32M16 (
+ output [1:0] DOA,
+ output [1:0] DOB,
+ output [1:0] DOC,
+ output [1:0] DOD,
+ output [1:0] DOE,
+ output [1:0] DOF,
+ output [1:0] DOG,
+ output [1:0] DOH,
+ input [4:0] ADDRA,
+ input [4:0] ADDRB,
+ input [4:0] ADDRC,
+ input [4:0] ADDRD,
+ input [4:0] ADDRE,
+ input [4:0] ADDRF,
+ input [4:0] ADDRG,
+ input [4:0] ADDRH,
+ input [1:0] DIA,
+ input [1:0] DIB,
+ input [1:0] DIC,
+ input [1:0] DID,
+ input [1:0] DIE,
+ input [1:0] DIF,
+ input [1:0] DIG,
+ input [1:0] DIH,
+ (* clkbuf_sink *)
+ (* invertible_pin = "IS_WCLK_INVERTED" *)
+ input WCLK,
+ input WE
+);
+ parameter [63:0] INIT_A = 64'h0000000000000000;
+ parameter [63:0] INIT_B = 64'h0000000000000000;
+ parameter [63:0] INIT_C = 64'h0000000000000000;
+ parameter [63:0] INIT_D = 64'h0000000000000000;
+ parameter [63:0] INIT_E = 64'h0000000000000000;
+ parameter [63:0] INIT_F = 64'h0000000000000000;
+ parameter [63:0] INIT_G = 64'h0000000000000000;
+ parameter [63:0] INIT_H = 64'h0000000000000000;
+ parameter [0:0] IS_WCLK_INVERTED = 1'b0;
+ reg [63:0] mem_a = INIT_A;
+ reg [63:0] mem_b = INIT_B;
+ reg [63:0] mem_c = INIT_C;
+ reg [63:0] mem_d = INIT_D;
+ reg [63:0] mem_e = INIT_E;
+ reg [63:0] mem_f = INIT_F;
+ reg [63:0] mem_g = INIT_G;
+ reg [63:0] mem_h = INIT_H;
+ assign DOA = mem_a[2*ADDRA+:2];
+ assign DOB = mem_b[2*ADDRB+:2];
+ assign DOC = mem_c[2*ADDRC+:2];
+ assign DOD = mem_d[2*ADDRD+:2];
+ assign DOE = mem_e[2*ADDRE+:2];
+ assign DOF = mem_f[2*ADDRF+:2];
+ assign DOG = mem_g[2*ADDRG+:2];
+ assign DOH = mem_h[2*ADDRH+:2];
+ wire clk = WCLK ^ IS_WCLK_INVERTED;
+ always @(posedge clk)
+ if (WE) begin
+ mem_a[2*ADDRH+:2] <= DIA;
+ mem_b[2*ADDRH+:2] <= DIB;
+ mem_c[2*ADDRH+:2] <= DIC;
+ mem_d[2*ADDRH+:2] <= DID;
+ mem_e[2*ADDRH+:2] <= DIE;
+ mem_f[2*ADDRH+:2] <= DIF;
+ mem_g[2*ADDRH+:2] <= DIG;
+ mem_h[2*ADDRH+:2] <= DIH;
+ end
+endmodule
+
+module RAM64M (
+ output DOA,
+ output DOB,
+ output DOC,
+ output DOD,
+ input [4:0] ADDRA,
+ input [4:0] ADDRB,
+ input [4:0] ADDRC,
+ input [4:0] ADDRD,
+ input DIA,
+ input DIB,
+ input DIC,
+ input DID,
+ (* clkbuf_sink *)
+ (* invertible_pin = "IS_WCLK_INVERTED" *)
+ input WCLK,
+ input WE
+);
+ parameter [63:0] INIT_A = 64'h0000000000000000;
+ parameter [63:0] INIT_B = 64'h0000000000000000;
+ parameter [63:0] INIT_C = 64'h0000000000000000;
+ parameter [63:0] INIT_D = 64'h0000000000000000;
+ parameter [0:0] IS_WCLK_INVERTED = 1'b0;
+ reg [63:0] mem_a = INIT_A;
+ reg [63:0] mem_b = INIT_B;
+ reg [63:0] mem_c = INIT_C;
+ reg [63:0] mem_d = INIT_D;
+ assign DOA = mem_a[ADDRA];
+ assign DOB = mem_b[ADDRB];
+ assign DOC = mem_c[ADDRC];
+ assign DOD = mem_d[ADDRD];
+ wire clk = WCLK ^ IS_WCLK_INVERTED;
+ always @(posedge clk)
+ if (WE) begin
+ mem_a[ADDRD] <= DIA;
+ mem_b[ADDRD] <= DIB;
+ mem_c[ADDRD] <= DIC;
+ mem_d[ADDRD] <= DID;
+ end
+endmodule
+
+module RAM64M8 (
+ output DOA,
+ output DOB,
+ output DOC,
+ output DOD,
+ output DOE,
+ output DOF,
+ output DOG,
+ output DOH,
+ input [4:0] ADDRA,
+ input [4:0] ADDRB,
+ input [4:0] ADDRC,
+ input [4:0] ADDRD,
+ input [4:0] ADDRE,
+ input [4:0] ADDRF,
+ input [4:0] ADDRG,
+ input [4:0] ADDRH,
+ input DIA,
+ input DIB,
+ input DIC,
+ input DID,
+ input DIE,
+ input DIF,
+ input DIG,
+ input DIH,
+ (* clkbuf_sink *)
+ (* invertible_pin = "IS_WCLK_INVERTED" *)
+ input WCLK,
+ input WE
+);
+ parameter [63:0] INIT_A = 64'h0000000000000000;
+ parameter [63:0] INIT_B = 64'h0000000000000000;
+ parameter [63:0] INIT_C = 64'h0000000000000000;
+ parameter [63:0] INIT_D = 64'h0000000000000000;
+ parameter [63:0] INIT_E = 64'h0000000000000000;
+ parameter [63:0] INIT_F = 64'h0000000000000000;
+ parameter [63:0] INIT_G = 64'h0000000000000000;
+ parameter [63:0] INIT_H = 64'h0000000000000000;
+ parameter [0:0] IS_WCLK_INVERTED = 1'b0;
+ reg [63:0] mem_a = INIT_A;
+ reg [63:0] mem_b = INIT_B;
+ reg [63:0] mem_c = INIT_C;
+ reg [63:0] mem_d = INIT_D;
+ reg [63:0] mem_e = INIT_E;
+ reg [63:0] mem_f = INIT_F;
+ reg [63:0] mem_g = INIT_G;
+ reg [63:0] mem_h = INIT_H;
+ assign DOA = mem_a[ADDRA];
+ assign DOB = mem_b[ADDRB];
+ assign DOC = mem_c[ADDRC];
+ assign DOD = mem_d[ADDRD];
+ assign DOE = mem_e[ADDRE];
+ assign DOF = mem_f[ADDRF];
+ assign DOG = mem_g[ADDRG];
+ assign DOH = mem_h[ADDRH];
+ wire clk = WCLK ^ IS_WCLK_INVERTED;
+ always @(posedge clk)
+ if (WE) begin
+ mem_a[ADDRH] <= DIA;
+ mem_b[ADDRH] <= DIB;
+ mem_c[ADDRH] <= DIC;
+ mem_d[ADDRH] <= DID;
+ mem_e[ADDRH] <= DIE;
+ mem_f[ADDRH] <= DIF;
+ mem_g[ADDRH] <= DIG;
+ mem_h[ADDRH] <= DIH;
+ end
+endmodule
+
+// ROM.
+
+module ROM16X1 (
+ output O,
+ input A0, A1, A2, A3
+);
+ parameter [15:0] INIT = 16'h0;
+ assign O = INIT[{A3, A2, A1, A0}];
+endmodule
+
+module ROM32X1 (
+ output O,
+ input A0, A1, A2, A3, A4
+);
+ parameter [31:0] INIT = 32'h0;
+ assign O = INIT[{A4, A3, A2, A1, A0}];
+endmodule
+
+module ROM64X1 (
+ output O,
+ input A0, A1, A2, A3, A4, A5
+);
+ parameter [63:0] INIT = 64'h0;
+ assign O = INIT[{A5, A4, A3, A2, A1, A0}];
+endmodule
+
+module ROM128X1 (
+ output O,
+ input A0, A1, A2, A3, A4, A5, A6
+);
+ parameter [127:0] INIT = 128'h0;
+ assign O = INIT[{A6, A5, A4, A3, A2, A1, A0}];
+endmodule
+
+module ROM256X1 (
+ output O,
+ input A0, A1, A2, A3, A4, A5, A6, A7
+);
+ parameter [255:0] INIT = 256'h0;
+ assign O = INIT[{A7, A6, A5, A4, A3, A2, A1, A0}];
+endmodule
+
+// Shift registers.
+
module SRL16E (
// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L904-L905
(* abc9_arrival=1472 *)
# - UG974 (Ultrascale)
# CLB -- RAM/ROM.
- Cell('RAM16X1S', port_attrs={'WCLK': ['clkbuf_sink']}),
- Cell('RAM16X1S_1', port_attrs={'WCLK': ['clkbuf_sink']}),
- Cell('RAM32X1S', port_attrs={'WCLK': ['clkbuf_sink']}),
- Cell('RAM32X1S_1', port_attrs={'WCLK': ['clkbuf_sink']}),
- Cell('RAM64X1S', port_attrs={'WCLK': ['clkbuf_sink']}),
- Cell('RAM64X1S_1', port_attrs={'WCLK': ['clkbuf_sink']}),
- Cell('RAM128X1S', port_attrs={'WCLK': ['clkbuf_sink']}),
- Cell('RAM128X1S_1', port_attrs={'WCLK': ['clkbuf_sink']}),
- Cell('RAM256X1S', port_attrs={'WCLK': ['clkbuf_sink']}),
- Cell('RAM512X1S', port_attrs={'WCLK': ['clkbuf_sink']}),
- Cell('RAM16X2S', port_attrs={'WCLK': ['clkbuf_sink']}),
- Cell('RAM32X2S', port_attrs={'WCLK': ['clkbuf_sink']}),
- Cell('RAM64X2S', port_attrs={'WCLK': ['clkbuf_sink']}),
- Cell('RAM16X4S', port_attrs={'WCLK': ['clkbuf_sink']}),
- Cell('RAM32X4S', port_attrs={'WCLK': ['clkbuf_sink']}),
- Cell('RAM16X8S', port_attrs={'WCLK': ['clkbuf_sink']}),
- Cell('RAM32X8S', port_attrs={'WCLK': ['clkbuf_sink']}),
- Cell('RAM16X1D', port_attrs={'WCLK': ['clkbuf_sink']}),
- Cell('RAM16X1D_1', port_attrs={'WCLK': ['clkbuf_sink']}),
- #Cell('RAM32X1D', port_attrs={'WCLK': ['clkbuf_sink']}),
- Cell('RAM32X1D_1', port_attrs={'WCLK': ['clkbuf_sink']}),
- #Cell('RAM64X1D', port_attrs={'WCLK': ['clkbuf_sink']}),
- Cell('RAM64X1D_1', port_attrs={'WCLK': ['clkbuf_sink']}),
- #Cell('RAM128X1D', port_attrs={'WCLK': ['clkbuf_sink']}),
- Cell('RAM256X1D', port_attrs={'WCLK': ['clkbuf_sink']}),
- Cell('RAM32M', port_attrs={'WCLK': ['clkbuf_sink']}),
- Cell('RAM32M16', port_attrs={'WCLK': ['clkbuf_sink']}),
- Cell('RAM64M', port_attrs={'WCLK': ['clkbuf_sink']}),
- Cell('RAM64M8', port_attrs={'WCLK': ['clkbuf_sink']}),
- Cell('ROM16X1'),
- Cell('ROM32X1'),
- Cell('ROM64X1'),
- Cell('ROM128X1'),
- Cell('ROM256X1'),
+ # Cell('RAM16X1S', port_attrs={'WCLK': ['clkbuf_sink']}),
+ # Cell('RAM16X1S_1', port_attrs={'WCLK': ['clkbuf_sink']}),
+ # Cell('RAM32X1S', port_attrs={'WCLK': ['clkbuf_sink']}),
+ # Cell('RAM32X1S_1', port_attrs={'WCLK': ['clkbuf_sink']}),
+ # Cell('RAM64X1S', port_attrs={'WCLK': ['clkbuf_sink']}),
+ # Cell('RAM64X1S_1', port_attrs={'WCLK': ['clkbuf_sink']}),
+ # Cell('RAM128X1S', port_attrs={'WCLK': ['clkbuf_sink']}),
+ # Cell('RAM128X1S_1', port_attrs={'WCLK': ['clkbuf_sink']}),
+ # Cell('RAM256X1S', port_attrs={'WCLK': ['clkbuf_sink']}),
+ # Cell('RAM512X1S', port_attrs={'WCLK': ['clkbuf_sink']}),
+ # Cell('RAM16X2S', port_attrs={'WCLK': ['clkbuf_sink']}),
+ # Cell('RAM32X2S', port_attrs={'WCLK': ['clkbuf_sink']}),
+ # Cell('RAM64X2S', port_attrs={'WCLK': ['clkbuf_sink']}),
+ # Cell('RAM16X4S', port_attrs={'WCLK': ['clkbuf_sink']}),
+ # Cell('RAM32X4S', port_attrs={'WCLK': ['clkbuf_sink']}),
+ # Cell('RAM16X8S', port_attrs={'WCLK': ['clkbuf_sink']}),
+ # Cell('RAM32X8S', port_attrs={'WCLK': ['clkbuf_sink']}),
+ # Cell('RAM16X1D', port_attrs={'WCLK': ['clkbuf_sink']}),
+ # Cell('RAM16X1D_1', port_attrs={'WCLK': ['clkbuf_sink']}),
+ # Cell('RAM32X1D', port_attrs={'WCLK': ['clkbuf_sink']}),
+ # Cell('RAM32X1D_1', port_attrs={'WCLK': ['clkbuf_sink']}),
+ # Cell('RAM64X1D', port_attrs={'WCLK': ['clkbuf_sink']}),
+ # Cell('RAM64X1D_1', port_attrs={'WCLK': ['clkbuf_sink']}),
+ # Cell('RAM128X1D', port_attrs={'WCLK': ['clkbuf_sink']}),
+ # Cell('RAM256X1D', port_attrs={'WCLK': ['clkbuf_sink']}),
+ # Cell('RAM32M', port_attrs={'WCLK': ['clkbuf_sink']}),
+ # Cell('RAM32M16', port_attrs={'WCLK': ['clkbuf_sink']}),
+ # Cell('RAM64M', port_attrs={'WCLK': ['clkbuf_sink']}),
+ # Cell('RAM64M8', port_attrs={'WCLK': ['clkbuf_sink']}),
+ # Cell('ROM16X1'),
+ # Cell('ROM32X1'),
+ # Cell('ROM64X1'),
+ # Cell('ROM128X1'),
+ # Cell('ROM256X1'),
# CLB -- registers/latches.
# Virtex 1/2/4/5, Spartan 3.
// Created by cells_xtra.py from Xilinx models
-module RAM16X1S (...);
- parameter [15:0] INIT = 16'h0000;
- parameter [0:0] IS_WCLK_INVERTED = 1'b0;
- output O;
- input A0;
- input A1;
- input A2;
- input A3;
- input D;
- (* clkbuf_sink *)
- (* invertible_pin = "IS_WCLK_INVERTED" *)
- input WCLK;
- input WE;
-endmodule
-
-module RAM16X1S_1 (...);
- parameter [15:0] INIT = 16'h0000;
- parameter [0:0] IS_WCLK_INVERTED = 1'b0;
- output O;
- input A0;
- input A1;
- input A2;
- input A3;
- input D;
- (* clkbuf_sink *)
- (* invertible_pin = "IS_WCLK_INVERTED" *)
- input WCLK;
- input WE;
-endmodule
-
-module RAM32X1S (...);
- parameter [31:0] INIT = 32'h00000000;
- parameter [0:0] IS_WCLK_INVERTED = 1'b0;
- output O;
- input A0;
- input A1;
- input A2;
- input A3;
- input A4;
- input D;
- (* clkbuf_sink *)
- (* invertible_pin = "IS_WCLK_INVERTED" *)
- input WCLK;
- input WE;
-endmodule
-
-module RAM32X1S_1 (...);
- parameter [31:0] INIT = 32'h00000000;
- parameter [0:0] IS_WCLK_INVERTED = 1'b0;
- output O;
- input A0;
- input A1;
- input A2;
- input A3;
- input A4;
- input D;
- (* clkbuf_sink *)
- (* invertible_pin = "IS_WCLK_INVERTED" *)
- input WCLK;
- input WE;
-endmodule
-
-module RAM64X1S (...);
- parameter [63:0] INIT = 64'h0000000000000000;
- parameter [0:0] IS_WCLK_INVERTED = 1'b0;
- output O;
- input A0;
- input A1;
- input A2;
- input A3;
- input A4;
- input A5;
- input D;
- (* clkbuf_sink *)
- (* invertible_pin = "IS_WCLK_INVERTED" *)
- input WCLK;
- input WE;
-endmodule
-
-module RAM64X1S_1 (...);
- parameter [63:0] INIT = 64'h0000000000000000;
- parameter [0:0] IS_WCLK_INVERTED = 1'b0;
- output O;
- input A0;
- input A1;
- input A2;
- input A3;
- input A4;
- input A5;
- input D;
- (* clkbuf_sink *)
- (* invertible_pin = "IS_WCLK_INVERTED" *)
- input WCLK;
- input WE;
-endmodule
-
-module RAM128X1S (...);
- parameter [127:0] INIT = 128'h00000000000000000000000000000000;
- parameter [0:0] IS_WCLK_INVERTED = 1'b0;
- output O;
- input A0;
- input A1;
- input A2;
- input A3;
- input A4;
- input A5;
- input A6;
- input D;
- (* clkbuf_sink *)
- (* invertible_pin = "IS_WCLK_INVERTED" *)
- input WCLK;
- input WE;
-endmodule
-
-module RAM128X1S_1 (...);
- parameter [127:0] INIT = 128'h00000000000000000000000000000000;
- parameter [0:0] IS_WCLK_INVERTED = 1'b0;
- output O;
- input A0;
- input A1;
- input A2;
- input A3;
- input A4;
- input A5;
- input A6;
- input D;
- (* clkbuf_sink *)
- (* invertible_pin = "IS_WCLK_INVERTED" *)
- input WCLK;
- input WE;
-endmodule
-
-module RAM256X1S (...);
- parameter [255:0] INIT = 256'h0;
- parameter [0:0] IS_WCLK_INVERTED = 1'b0;
- output O;
- input [7:0] A;
- input D;
- (* clkbuf_sink *)
- (* invertible_pin = "IS_WCLK_INVERTED" *)
- input WCLK;
- input WE;
-endmodule
-
-module RAM512X1S (...);
- parameter [511:0] INIT = 512'h0;
- parameter [0:0] IS_WCLK_INVERTED = 1'b0;
- output O;
- input [8:0] A;
- input D;
- (* clkbuf_sink *)
- (* invertible_pin = "IS_WCLK_INVERTED" *)
- input WCLK;
- input WE;
-endmodule
-
-module RAM16X2S (...);
- parameter [15:0] INIT_00 = 16'h0000;
- parameter [15:0] INIT_01 = 16'h0000;
- parameter [0:0] IS_WCLK_INVERTED = 1'b0;
- output O0;
- output O1;
- input A0;
- input A1;
- input A2;
- input A3;
- input D0;
- input D1;
- (* clkbuf_sink *)
- (* invertible_pin = "IS_WCLK_INVERTED" *)
- input WCLK;
- input WE;
-endmodule
-
-module RAM32X2S (...);
- parameter [31:0] INIT_00 = 32'h00000000;
- parameter [31:0] INIT_01 = 32'h00000000;
- parameter [0:0] IS_WCLK_INVERTED = 1'b0;
- output O0;
- output O1;
- input A0;
- input A1;
- input A2;
- input A3;
- input A4;
- input D0;
- input D1;
- (* clkbuf_sink *)
- (* invertible_pin = "IS_WCLK_INVERTED" *)
- input WCLK;
- input WE;
-endmodule
-
-module RAM64X2S (...);
- parameter [63:0] INIT_00 = 64'h0000000000000000;
- parameter [63:0] INIT_01 = 64'h0000000000000000;
- parameter [0:0] IS_WCLK_INVERTED = 1'b0;
- output O0;
- output O1;
- input A0;
- input A1;
- input A2;
- input A3;
- input A4;
- input A5;
- input D0;
- input D1;
- (* clkbuf_sink *)
- (* invertible_pin = "IS_WCLK_INVERTED" *)
- input WCLK;
- input WE;
-endmodule
-
-module RAM16X4S (...);
- parameter [15:0] INIT_00 = 16'h0000;
- parameter [15:0] INIT_01 = 16'h0000;
- parameter [15:0] INIT_02 = 16'h0000;
- parameter [15:0] INIT_03 = 16'h0000;
- parameter [0:0] IS_WCLK_INVERTED = 1'b0;
- output O0;
- output O1;
- output O2;
- output O3;
- input A0;
- input A1;
- input A2;
- input A3;
- input D0;
- input D1;
- input D2;
- input D3;
- (* clkbuf_sink *)
- (* invertible_pin = "IS_WCLK_INVERTED" *)
- input WCLK;
- input WE;
-endmodule
-
-module RAM32X4S (...);
- parameter [31:0] INIT_00 = 32'h00000000;
- parameter [31:0] INIT_01 = 32'h00000000;
- parameter [31:0] INIT_02 = 32'h00000000;
- parameter [31:0] INIT_03 = 32'h00000000;
- parameter [0:0] IS_WCLK_INVERTED = 1'b0;
- output O0;
- output O1;
- output O2;
- output O3;
- input A0;
- input A1;
- input A2;
- input A3;
- input A4;
- input D0;
- input D1;
- input D2;
- input D3;
- (* clkbuf_sink *)
- (* invertible_pin = "IS_WCLK_INVERTED" *)
- input WCLK;
- input WE;
-endmodule
-
-module RAM16X8S (...);
- parameter [15:0] INIT_00 = 16'h0000;
- parameter [15:0] INIT_01 = 16'h0000;
- parameter [15:0] INIT_02 = 16'h0000;
- parameter [15:0] INIT_03 = 16'h0000;
- parameter [15:0] INIT_04 = 16'h0000;
- parameter [15:0] INIT_05 = 16'h0000;
- parameter [15:0] INIT_06 = 16'h0000;
- parameter [15:0] INIT_07 = 16'h0000;
- parameter [0:0] IS_WCLK_INVERTED = 1'b0;
- output [7:0] O;
- input A0;
- input A1;
- input A2;
- input A3;
- (* clkbuf_sink *)
- (* invertible_pin = "IS_WCLK_INVERTED" *)
- input WCLK;
- input WE;
- input [7:0] D;
-endmodule
-
-module RAM32X8S (...);
- parameter [31:0] INIT_00 = 32'h00000000;
- parameter [31:0] INIT_01 = 32'h00000000;
- parameter [31:0] INIT_02 = 32'h00000000;
- parameter [31:0] INIT_03 = 32'h00000000;
- parameter [31:0] INIT_04 = 32'h00000000;
- parameter [31:0] INIT_05 = 32'h00000000;
- parameter [31:0] INIT_06 = 32'h00000000;
- parameter [31:0] INIT_07 = 32'h00000000;
- parameter [0:0] IS_WCLK_INVERTED = 1'b0;
- output [7:0] O;
- input A0;
- input A1;
- input A2;
- input A3;
- input A4;
- (* clkbuf_sink *)
- (* invertible_pin = "IS_WCLK_INVERTED" *)
- input WCLK;
- input WE;
- input [7:0] D;
-endmodule
-
-module RAM16X1D (...);
- parameter [15:0] INIT = 16'h0000;
- parameter [0:0] IS_WCLK_INVERTED = 1'b0;
- output DPO;
- output SPO;
- input A0;
- input A1;
- input A2;
- input A3;
- input D;
- input DPRA0;
- input DPRA1;
- input DPRA2;
- input DPRA3;
- (* clkbuf_sink *)
- (* invertible_pin = "IS_WCLK_INVERTED" *)
- input WCLK;
- input WE;
-endmodule
-
-module RAM16X1D_1 (...);
- parameter [15:0] INIT = 16'h0000;
- parameter [0:0] IS_WCLK_INVERTED = 1'b0;
- output DPO;
- output SPO;
- input A0;
- input A1;
- input A2;
- input A3;
- input D;
- input DPRA0;
- input DPRA1;
- input DPRA2;
- input DPRA3;
- (* clkbuf_sink *)
- (* invertible_pin = "IS_WCLK_INVERTED" *)
- input WCLK;
- input WE;
-endmodule
-
-module RAM32X1D_1 (...);
- parameter [31:0] INIT = 32'h00000000;
- parameter [0:0] IS_WCLK_INVERTED = 1'b0;
- output DPO;
- output SPO;
- input A0;
- input A1;
- input A2;
- input A3;
- input A4;
- input D;
- input DPRA0;
- input DPRA1;
- input DPRA2;
- input DPRA3;
- input DPRA4;
- (* clkbuf_sink *)
- (* invertible_pin = "IS_WCLK_INVERTED" *)
- input WCLK;
- input WE;
-endmodule
-
-module RAM64X1D_1 (...);
- parameter [63:0] INIT = 64'h0000000000000000;
- parameter [0:0] IS_WCLK_INVERTED = 1'b0;
- output DPO;
- output SPO;
- input A0;
- input A1;
- input A2;
- input A3;
- input A4;
- input A5;
- input D;
- input DPRA0;
- input DPRA1;
- input DPRA2;
- input DPRA3;
- input DPRA4;
- input DPRA5;
- (* clkbuf_sink *)
- (* invertible_pin = "IS_WCLK_INVERTED" *)
- input WCLK;
- input WE;
-endmodule
-
-module RAM256X1D (...);
- parameter [255:0] INIT = 256'h0000000000000000000000000000000000000000000000000000000000000000;
- parameter [0:0] IS_WCLK_INVERTED = 1'b0;
- output DPO;
- output SPO;
- input [7:0] A;
- input D;
- input [7:0] DPRA;
- (* clkbuf_sink *)
- (* invertible_pin = "IS_WCLK_INVERTED" *)
- input WCLK;
- input WE;
-endmodule
-
-module RAM32M (...);
- parameter [63:0] INIT_A = 64'h0000000000000000;
- parameter [63:0] INIT_B = 64'h0000000000000000;
- parameter [63:0] INIT_C = 64'h0000000000000000;
- parameter [63:0] INIT_D = 64'h0000000000000000;
- parameter [0:0] IS_WCLK_INVERTED = 1'b0;
- output [1:0] DOA;
- output [1:0] DOB;
- output [1:0] DOC;
- output [1:0] DOD;
- input [4:0] ADDRA;
- input [4:0] ADDRB;
- input [4:0] ADDRC;
- input [4:0] ADDRD;
- input [1:0] DIA;
- input [1:0] DIB;
- input [1:0] DIC;
- input [1:0] DID;
- (* clkbuf_sink *)
- (* invertible_pin = "IS_WCLK_INVERTED" *)
- input WCLK;
- input WE;
-endmodule
-
-module RAM32M16 (...);
- parameter [63:0] INIT_A = 64'h0000000000000000;
- parameter [63:0] INIT_B = 64'h0000000000000000;
- parameter [63:0] INIT_C = 64'h0000000000000000;
- parameter [63:0] INIT_D = 64'h0000000000000000;
- parameter [63:0] INIT_E = 64'h0000000000000000;
- parameter [63:0] INIT_F = 64'h0000000000000000;
- parameter [63:0] INIT_G = 64'h0000000000000000;
- parameter [63:0] INIT_H = 64'h0000000000000000;
- parameter [0:0] IS_WCLK_INVERTED = 1'b0;
- output [1:0] DOA;
- output [1:0] DOB;
- output [1:0] DOC;
- output [1:0] DOD;
- output [1:0] DOE;
- output [1:0] DOF;
- output [1:0] DOG;
- output [1:0] DOH;
- input [4:0] ADDRA;
- input [4:0] ADDRB;
- input [4:0] ADDRC;
- input [4:0] ADDRD;
- input [4:0] ADDRE;
- input [4:0] ADDRF;
- input [4:0] ADDRG;
- input [4:0] ADDRH;
- input [1:0] DIA;
- input [1:0] DIB;
- input [1:0] DIC;
- input [1:0] DID;
- input [1:0] DIE;
- input [1:0] DIF;
- input [1:0] DIG;
- input [1:0] DIH;
- (* clkbuf_sink *)
- (* invertible_pin = "IS_WCLK_INVERTED" *)
- input WCLK;
- input WE;
-endmodule
-
-module RAM64M (...);
- parameter [63:0] INIT_A = 64'h0000000000000000;
- parameter [63:0] INIT_B = 64'h0000000000000000;
- parameter [63:0] INIT_C = 64'h0000000000000000;
- parameter [63:0] INIT_D = 64'h0000000000000000;
- parameter [0:0] IS_WCLK_INVERTED = 1'b0;
- output DOA;
- output DOB;
- output DOC;
- output DOD;
- input [5:0] ADDRA;
- input [5:0] ADDRB;
- input [5:0] ADDRC;
- input [5:0] ADDRD;
- input DIA;
- input DIB;
- input DIC;
- input DID;
- (* clkbuf_sink *)
- (* invertible_pin = "IS_WCLK_INVERTED" *)
- input WCLK;
- input WE;
-endmodule
-
-module RAM64M8 (...);
- parameter [63:0] INIT_A = 64'h0000000000000000;
- parameter [63:0] INIT_B = 64'h0000000000000000;
- parameter [63:0] INIT_C = 64'h0000000000000000;
- parameter [63:0] INIT_D = 64'h0000000000000000;
- parameter [63:0] INIT_E = 64'h0000000000000000;
- parameter [63:0] INIT_F = 64'h0000000000000000;
- parameter [63:0] INIT_G = 64'h0000000000000000;
- parameter [63:0] INIT_H = 64'h0000000000000000;
- parameter [0:0] IS_WCLK_INVERTED = 1'b0;
- output DOA;
- output DOB;
- output DOC;
- output DOD;
- output DOE;
- output DOF;
- output DOG;
- output DOH;
- input [5:0] ADDRA;
- input [5:0] ADDRB;
- input [5:0] ADDRC;
- input [5:0] ADDRD;
- input [5:0] ADDRE;
- input [5:0] ADDRF;
- input [5:0] ADDRG;
- input [5:0] ADDRH;
- input DIA;
- input DIB;
- input DIC;
- input DID;
- input DIE;
- input DIF;
- input DIG;
- input DIH;
- (* clkbuf_sink *)
- (* invertible_pin = "IS_WCLK_INVERTED" *)
- input WCLK;
- input WE;
-endmodule
-
-module ROM16X1 (...);
- parameter [127:0] INIT = 16'h0000;
- output O;
- input A0;
- input A1;
- input A2;
- input A3;
-endmodule
-
-module ROM32X1 (...);
- parameter [31:0] INIT = 32'h00000000;
- output O;
- input A0;
- input A1;
- input A2;
- input A3;
- input A4;
-endmodule
-
-module ROM64X1 (...);
- parameter [63:0] INIT = 64'h0000000000000000;
- output O;
- input A0;
- input A1;
- input A2;
- input A3;
- input A4;
- input A5;
-endmodule
-
-module ROM128X1 (...);
- parameter [127:0] INIT = 128'h00000000000000000000000000000000;
- output O;
- input A0;
- input A1;
- input A2;
- input A3;
- input A4;
- input A5;
- input A6;
-endmodule
-
-module ROM256X1 (...);
- parameter [255:0] INIT = 256'h0000000000000000000000000000000000000000000000000000000000000000;
- output O;
- input A0;
- input A1;
- input A2;
- input A3;
- input A4;
- input A5;
- input A6;
- input A7;
-endmodule
-
module FDCPE (...);
parameter [0:0] INIT = 1'b0;
parameter [0:0] IS_C_INVERTED = 1'b0;
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