AARCH64: ILP32: Fix aarch64_asan_shadow_offset

aarch64_asan_shadow_offset is using the wrong
offset for ILP32.  Change it to be a decent one.

ChangeLog:
* config/aarch64/aarch64.c (aarch64_asan_shadow_offset):
Fix ILP32 value.

From-SVN: r271920

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 61299f2cad75dc0643c9f2377c5b52e8a10ada4f..70d1b7d968c955e6401314ee70bcd070d72127da 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,8 @@
+2019-06-04  Andrew Pinski  <apinski@marvell.com>
+
+       * config/aarch64/aarch64.c (aarch64_asan_shadow_offset):
+       Fix ILP32 value.
+
 2019-06-04  Segher Boessenkool  <segher@kernel.crashing.org>
 
        * config/rs6000/constraints.md (define_register_constraint "wd"):

diff --git a/gcc/config/aarch64/aarch64.c b/gcc/config/aarch64/aarch64.c
index 7acc3227a781d8aa4a152d83e8572b079acb42a2..b3c42e210c5f506983e6a312259815f9906e5532 100644 (file)
--- a/gcc/config/aarch64/aarch64.c
+++ b/gcc/config/aarch64/aarch64.c
@@ -17574,7 +17574,10 @@ aarch64_expand_subvti (rtx op0, rtx low_dest, rtx low_in1,
 static unsigned HOST_WIDE_INT
 aarch64_asan_shadow_offset (void)
 {
-  return (HOST_WIDE_INT_1 << 36);
+  if (TARGET_ILP32)
+    return (HOST_WIDE_INT_1 << 29);
+  else
+    return (HOST_WIDE_INT_1 << 36);
 }
 
 static rtx