fprintf(stderr, "disabling 3D acceleration\n");
FALLBACK(rmesa, R200_FALLBACK_DISABLE, 1);
}
- else if (tcl_mode == DRI_CONF_TCL_SW || getenv("R200_NO_TCL")) {
+ else if (tcl_mode == DRI_CONF_TCL_SW || getenv("R200_NO_TCL") ||
+ !(rmesa->r200Screen->chipset & R200_CHIPSET_TCL)) {
fprintf(stderr, "disabling TCL support\n");
TCL_FALLBACK(rmesa->glCtx, R200_TCL_FALLBACK_TCL_DISABLE, 1);
}
- else {
+ if (rmesa->r200Screen->chipset & R200_CHIPSET_TCL) {
if (tcl_mode >= DRI_CONF_TCL_VTXFMT && !getenv("R200_NO_VTXFMT")) {
r200VtxfmtInit( ctx, tcl_mode >= DRI_CONF_TCL_CODEGEN );
}
#define PCI_CHIP_R200_LY 0x4C59
#define PCI_CHIP_R200_LZ 0x4C5A
#define PCI_CHIP_RV200_QW 0x5157 /* Radeon 7500 - not an R200 at all */
+#define PCI_CHIP_RS100_4136 0x4136 /* IGP RS100, RS200, RS250 are not R200 */
+#define PCI_CHIP_RS200_4137 0x4137
+#define PCI_CHIP_RS250_4237 0x4237
+#define PCI_CHIP_RS100_4336 0x4336
+#define PCI_CHIP_RS200_4337 0x4337
+#define PCI_CHIP_RS250_4437 0x4437
+#define PCI_CHIP_RS300_5834 0x5834 /* All RS300's are R200 */
+#define PCI_CHIP_RS300_5835 0x5835
+#define PCI_CHIP_RS300_5836 0x5836
+#define PCI_CHIP_RS300_5837 0x5837
#endif
static r200ScreenPtr __r200Screen;
return NULL;
}
+ screen->chipset = 0;
switch ( dri_priv->deviceID ) {
case PCI_CHIP_R200_QD:
case PCI_CHIP_R200_QE:
case PCI_CHIP_R200_LW:
case PCI_CHIP_R200_LY:
case PCI_CHIP_R200_LZ:
+ case PCI_CHIP_RS100_4136:
+ case PCI_CHIP_RS200_4137:
+ case PCI_CHIP_RS250_4237:
+ case PCI_CHIP_RS100_4336:
+ case PCI_CHIP_RS200_4337:
+ case PCI_CHIP_RS250_4437:
__driUtilMessage("r200CreateScreen(): Device isn't an r200!\n");
FREE( screen );
- return NULL;
+ return NULL;
+
+ case PCI_CHIP_RS300_5834:
+ case PCI_CHIP_RS300_5835:
+ case PCI_CHIP_RS300_5836:
+ case PCI_CHIP_RS300_5837:
+ break;
+
default:
- screen->chipset = R200_CHIPSET_R200;
+ screen->chipset |= R200_CHIPSET_TCL;
break;
}
drmAddress map; /* Mapping of the DRM region */
} r200RegionRec, *r200RegionPtr;
-#define R200_CHIPSET_R200 1
-#define R200_CHIPSET_MOBILITY 2
+
+/* chipset features */
+#define R200_CHIPSET_TCL (1 << 0)
#define R200_NR_TEX_HEAPS 2
#else
R200_VC_NO_SWAP;
#endif
+
+ if (!(rmesa->r200Screen->chipset & R200_CHIPSET_TCL)) {
+ /* Bypass TCL */
+ rmesa->hw.cst.cmd[CST_SE_VAP_CNTL_STATUS] |= (1<<8);
+ }
+
rmesa->hw.cst.cmd[CST_RE_POINTSIZE] = 0x100010;
rmesa->hw.cst.cmd[CST_SE_TCL_INPUT_VTX_0] =
(0x0 << R200_VERTEX_POSITION_ADDR__SHIFT);
#define PCI_CHIP_RADEON_LZ 0x4C5A
#define PCI_CHIP_RV200_QW 0x5157 /* Radeon 7500 - not an R200 at all */
+/* IGP Chipsets */
+#define PCI_CHIP_RS100_4136 0x4136
+#define PCI_CHIP_RS200_4137 0x4137
+#define PCI_CHIP_RS250_4237 0x4237
+#define PCI_CHIP_RS100_4336 0x4336
+#define PCI_CHIP_RS200_4337 0x4337
+#define PCI_CHIP_RS250_4437 0x4437
#endif
static int getSwapInfo( __DRIdrawablePrivate *dPriv, __DRIswapInfo * sInfo );
case PCI_CHIP_RADEON_QZ:
case PCI_CHIP_RADEON_LY:
case PCI_CHIP_RADEON_LZ:
+ case PCI_CHIP_RS100_4136: /* IGPs don't have TCL */
+ case PCI_CHIP_RS200_4137:
+ case PCI_CHIP_RS250_4237:
+ case PCI_CHIP_RS100_4336:
+ case PCI_CHIP_RS200_4337:
+ case PCI_CHIP_RS250_4437:
break;
}