test-insttest-rv64i-linux-DerivO3CPU-RISCV-aarch64-fast
test-insttest-linux-AtomicSimpleCPU-SPARC-aarch64-fast
test-insttest-linux-TimingSimpleCPU-SPARC-aarch64-fast
-test-atomic-DerivO3CPU-SPARC-x86_64-opt
-test-atomic-TimingSimpleCPU-SPARC-x86_64-opt
-test-atomic-DerivO3CPU-SPARC-x86_64-debug
-test-atomic-TimingSimpleCPU-SPARC-x86_64-debug
-test-atomic-DerivO3CPU-SPARC-x86_64-fast
-test-atomic-TimingSimpleCPU-SPARC-x86_64-fast
-test-atomic-DerivO3CPU-SPARC-aarch64-opt
-test-atomic-TimingSimpleCPU-SPARC-aarch64-opt
-test-atomic-DerivO3CPU-SPARC-aarch64-debug
-test-atomic-TimingSimpleCPU-SPARC-aarch64-debug
-test-atomic-DerivO3CPU-SPARC-aarch64-fast
-test-atomic-TimingSimpleCPU-SPARC-aarch64-fast
realview-o3-checker-ARM-x86_64-opt
realview64-o3-checker-ARM-x86_64-opt
import m5
from m5.objects import *
+from caches import *
import sys
import argparse
root.system.clk_domain.clock = '3GHz'
root.system.clk_domain.voltage_domain = VoltageDomain()
root.system.mem_mode = 'timing'
+root.system.mem_ranges = [AddrRange('512MB')]
if args.cpu_type == 'DerivO3CPU':
root.system.cpu = [DerivO3CPU(cpu_id = i)
print("ERROR: CPU Type '" + args.cpu_type + "' not supported")
sys.exit(1)
+root.system.membus = SystemXBar()
+root.system.membus.badaddr_responder = BadAddr()
+root.system.membus.default = root.system.membus.badaddr_responder.pio
+
+root.system.system_port = root.system.membus.slave
+
process = Process(executable = args.cmd,
cmd = [args.cmd, str(args.num_cores)])
-for i in range(int(args.num_cores)):
- root.system.cpu[i].workload = process
+for cpu in root.system.cpu:
+ cpu.workload = process
+ cpu.createThreads()
+ cpu.createInterruptController()
+
+ # Create a memory bus, a coherent crossbar, in this case
+ cpu.l2bus = L2XBar()
+
+ # Create an L1 instruction and data cache
+ cpu.icache = L1ICache()
+ cpu.dcache = L1DCache()
+
+ # Connect the instruction and data caches to the CPU
+ cpu.icache.connectCPU(cpu)
+ cpu.dcache.connectCPU(cpu)
+
+ # Hook the CPU ports up to the l2bus
+ cpu.icache.connectBus(cpu.l2bus)
+ cpu.dcache.connectBus(cpu.l2bus)
+
+ # Create an L2 cache and connect it to the l2bus
+ cpu.l2cache = L2Cache()
+ cpu.l2cache.connectCPUSideBus(cpu.l2bus)
+
+ # Connect the L2 cache to the L3 bus
+ cpu.l2cache.connectMemSideBus(root.system.membus)
+
+root.system.mem_ctrl = DDR3_1600_8x8()
+root.system.mem_ctrl.range = root.system.mem_ranges[0]
+root.system.mem_ctrl.port = root.system.membus.master
m5.instantiate()
exit_event = m5.simulate()
--- /dev/null
+# Copyright (c) 2016 Jason Lowe-Power
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+""" Caches with options for a simple gem5 configuration script
+
+This file contains L1 I/D and L2 caches to be used in the simple
+gem5 configuration script.
+"""
+
+import m5
+from m5.objects import Cache, L2XBar, StridePrefetcher, SubSystem
+from m5.params import AddrRange, AllMemory, MemorySize
+from m5.util.convert import toMemorySize
+
+# Some specific options for caches
+# For all options see src/mem/cache/BaseCache.py
+
+
+class L1Cache(PrefetchCache):
+ """Simple L1 Cache with default values"""
+
+ assoc = 8
+ tag_latency = 1
+ data_latency = 1
+ response_latency = 1
+ mshrs = 16
+ tgts_per_mshr = 20
+ writeback_clean = True
+
+ def __init__(self, options=None):
+ super(L1Cache, self).__init__(options)
+ pass
+
+ def connectBus(self, bus):
+ """Connect this cache to a memory-side bus"""
+ self.mem_side = bus.slave
+
+ def connectCPU(self, cpu):
+ """Connect this cache's port to a CPU-side port
+ This must be defined in a subclass"""
+ raise NotImplementedError
+
+class L1ICache(L1Cache):
+ """Simple L1 instruction cache with default values"""
+
+ # Set the size
+ size = '32kB'
+
+ def __init__(self, opts=None):
+ super(L1ICache, self).__init__(opts)
+
+ def connectCPU(self, cpu):
+ """Connect this cache's port to a CPU icache port"""
+ self.cpu_side = cpu.icache_port
+
+class L1DCache(L1Cache):
+ """Simple L1 data cache with default values"""
+
+ # Set the size
+ size = '32kB'
+
+ def __init__(self, opts=None):
+ super(L1DCache, self).__init__(opts)
+
+ def connectCPU(self, cpu):
+ """Connect this cache's port to a CPU dcache port"""
+ self.cpu_side = cpu.dcache_port
+
+class L2Cache(PrefetchCache):
+ """Simple L2 Cache with default values"""
+
+ # Default parameters
+ size = '256kB'
+ assoc = 16
+ tag_latency = 10
+ data_latency = 10
+ response_latency = 1
+ mshrs = 20
+ tgts_per_mshr = 12
+ writeback_clean = True
+
+ def __init__(self, opts=None):
+ super(L2Cache, self).__init__(opts)
+
+ def connectCPUSideBus(self, bus):
+ self.cpu_side = bus.master
+
+ def connectMemSideBus(self, bus):
+ self.mem_side = bus.slave
+++ /dev/null
-Redirecting stdout to build/SPARC/tests/opt/quick/se/40.m5threads-test-atomic/sparc/linux/o3-timing-mp/simout
-Redirecting stderr to build/SPARC/tests/opt/quick/se/40.m5threads-test-atomic/sparc/linux/o3-timing-mp/simerr
-gem5 Simulator System. http://gem5.org
-gem5 is copyrighted software; use the --copyright option for details.
-
-gem5 compiled Mar 29 2017 21:12:17
-gem5 started Mar 29 2017 21:12:27
-gem5 executing on gabeblack-desktop.mtv.corp.google.com, pid 42630
-command line: /usr/local/google/home/gabeblack/gem5/gem5-public/build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/40.m5threads-test-atomic/sparc/linux/o3-timing-mp --stats-file 'text://stats.txt?desc=False' -re /usr/local/google/home/gabeblack/gem5/gem5-public/tests/testing/../run.py quick/se/40.m5threads-test-atomic/sparc/linux/o3-timing-mp
-
-Global frequency set at 1000000000000 ticks per second
-Init done
-[Iteration 1, Thread 1] Got lock
-[Iteration 1, Thread 1] Critical section done, previously next=0, now next=1
-[Iteration 1, Thread 3] Got lock
-[Iteration 1, Thread 3] Critical section done, previously next=1, now next=3
-[Iteration 1, Thread 2] Got lock
-[Iteration 1, Thread 2] Critical section done, previously next=3, now next=2
-Iteration 1 completed
-[Iteration 2, Thread 3] Got lock
-[Iteration 2, Thread 3] Critical section done, previously next=0, now next=3
-[Iteration 2, Thread 2] Got lock
-[Iteration 2, Thread 2] Critical section done, previously next=3, now next=2
-[Iteration 2, Thread 1] Got lock
-[Iteration 2, Thread 1] Critical section done, previously next=2, now next=1
-Iteration 2 completed
-[Iteration 3, Thread 2] Got lock
-[Iteration 3, Thread 2] Critical section done, previously next=0, now next=2
-[Iteration 3, Thread 3] Got lock
-[Iteration 3, Thread 3] Critical section done, previously next=2, now next=3
-[Iteration 3, Thread 1] Got lock
-[Iteration 3, Thread 1] Critical section done, previously next=3, now next=1
-Iteration 3 completed
-[Iteration 4, Thread 1] Got lock
-[Iteration 4, Thread 1] Critical section done, previously next=0, now next=1
-[Iteration 4, Thread 3] Got lock
-[Iteration 4, Thread 3] Critical section done, previously next=1, now next=3
-[Iteration 4, Thread 2] Got lock
-[Iteration 4, Thread 2] Critical section done, previously next=3, now next=2
-Iteration 4 completed
-[Iteration 5, Thread 1] Got lock
-[Iteration 5, Thread 1] Critical section done, previously next=0, now next=1
-[Iteration 5, Thread 2] Got lock
-[Iteration 5, Thread 2] Critical section done, previously next=1, now next=2
-[Iteration 5, Thread 3] Got lock
-[Iteration 5, Thread 3] Critical section done, previously next=2, now next=3
-Iteration 5 completed
-[Iteration 6, Thread 3] Got lock
-[Iteration 6, Thread 3] Critical section done, previously next=0, now next=3
-[Iteration 6, Thread 2] Got lock
-[Iteration 6, Thread 2] Critical section done, previously next=3, now next=2
-[Iteration 6, Thread 1] Got lock
-[Iteration 6, Thread 1] Critical section done, previously next=2, now next=1
-Iteration 6 completed
-[Iteration 7, Thread 3] Got lock
-[Iteration 7, Thread 3] Critical section done, previously next=0, now next=3
-[Iteration 7, Thread 2] Got lock
-[Iteration 7, Thread 2] Critical section done, previously next=3, now next=2
-[Iteration 7, Thread 1] Got lock
-[Iteration 7, Thread 1] Critical section done, previously next=2, now next=1
-Iteration 7 completed
-[Iteration 8, Thread 3] Got lock
-[Iteration 8, Thread 3] Critical section done, previously next=0, now next=3
-[Iteration 8, Thread 2] Got lock
-[Iteration 8, Thread 2] Critical section done, previously next=3, now next=2
-[Iteration 8, Thread 1] Got lock
-[Iteration 8, Thread 1] Critical section done, previously next=2, now next=1
-Iteration 8 completed
-[Iteration 9, Thread 1] Got lock
-[Iteration 9, Thread 1] Critical section done, previously next=0, now next=1
-[Iteration 9, Thread 2] Got lock
-[Iteration 9, Thread 2] Critical section done, previously next=1, now next=2
-[Iteration 9, Thread 3] Got lock
-[Iteration 9, Thread 3] Critical section done, previously next=2, now next=3
-Iteration 9 completed
-[Iteration 10, Thread 3] Got lock
-[Iteration 10, Thread 3] Critical section done, previously next=0, now next=3
-[Iteration 10, Thread 2] Got lock
-[Iteration 10, Thread 2] Critical section done, previously next=3, now next=2
-[Iteration 10, Thread 1] Got lock
-[Iteration 10, Thread 1] Critical section done, previously next=2, now next=1
-Iteration 10 completed
-PASSED :-)
-Exiting @ tick 126524000 because exiting with last active thread context
--- /dev/null
+gem5 Simulator System. http://gem5.org
+gem5 is copyrighted software; use the --copyright option for details.
+
+
+Global frequency set at 1000000000000 ticks per second
+Init done
+[Iteration 1, Thread 1] Got lock
+[Iteration 1, Thread 1] Critical section done, previously next=0, now next=1
+[Iteration 1, Thread 3] Got lock
+[Iteration 1, Thread 3] Critical section done, previously next=1, now next=3
+[Iteration 1, Thread 2] Got lock
+[Iteration 1, Thread 2] Critical section done, previously next=3, now next=2
+Iteration 1 completed
+[Iteration 2, Thread 3] Got lock
+[Iteration 2, Thread 3] Critical section done, previously next=0, now next=3
+[Iteration 2, Thread 2] Got lock
+[Iteration 2, Thread 2] Critical section done, previously next=3, now next=2
+[Iteration 2, Thread 1] Got lock
+[Iteration 2, Thread 1] Critical section done, previously next=2, now next=1
+Iteration 2 completed
+[Iteration 3, Thread 2] Got lock
+[Iteration 3, Thread 2] Critical section done, previously next=0, now next=2
+[Iteration 3, Thread 3] Got lock
+[Iteration 3, Thread 3] Critical section done, previously next=2, now next=3
+[Iteration 3, Thread 1] Got lock
+[Iteration 3, Thread 1] Critical section done, previously next=3, now next=1
+Iteration 3 completed
+[Iteration 4, Thread 1] Got lock
+[Iteration 4, Thread 1] Critical section done, previously next=0, now next=1
+[Iteration 4, Thread 3] Got lock
+[Iteration 4, Thread 3] Critical section done, previously next=1, now next=3
+[Iteration 4, Thread 2] Got lock
+[Iteration 4, Thread 2] Critical section done, previously next=3, now next=2
+Iteration 4 completed
+[Iteration 5, Thread 1] Got lock
+[Iteration 5, Thread 1] Critical section done, previously next=0, now next=1
+[Iteration 5, Thread 2] Got lock
+[Iteration 5, Thread 2] Critical section done, previously next=1, now next=2
+[Iteration 5, Thread 3] Got lock
+[Iteration 5, Thread 3] Critical section done, previously next=2, now next=3
+Iteration 5 completed
+[Iteration 6, Thread 3] Got lock
+[Iteration 6, Thread 3] Critical section done, previously next=0, now next=3
+[Iteration 6, Thread 2] Got lock
+[Iteration 6, Thread 2] Critical section done, previously next=3, now next=2
+[Iteration 6, Thread 1] Got lock
+[Iteration 6, Thread 1] Critical section done, previously next=2, now next=1
+Iteration 6 completed
+[Iteration 7, Thread 3] Got lock
+[Iteration 7, Thread 3] Critical section done, previously next=0, now next=3
+[Iteration 7, Thread 2] Got lock
+[Iteration 7, Thread 2] Critical section done, previously next=3, now next=2
+[Iteration 7, Thread 1] Got lock
+[Iteration 7, Thread 1] Critical section done, previously next=2, now next=1
+Iteration 7 completed
+[Iteration 8, Thread 3] Got lock
+[Iteration 8, Thread 3] Critical section done, previously next=0, now next=3
+[Iteration 8, Thread 2] Got lock
+[Iteration 8, Thread 2] Critical section done, previously next=3, now next=2
+[Iteration 8, Thread 1] Got lock
+[Iteration 8, Thread 1] Critical section done, previously next=2, now next=1
+Iteration 8 completed
+[Iteration 9, Thread 1] Got lock
+[Iteration 9, Thread 1] Critical section done, previously next=0, now next=1
+[Iteration 9, Thread 2] Got lock
+[Iteration 9, Thread 2] Critical section done, previously next=1, now next=2
+[Iteration 9, Thread 3] Got lock
+[Iteration 9, Thread 3] Critical section done, previously next=2, now next=3
+Iteration 9 completed
+[Iteration 10, Thread 3] Got lock
+[Iteration 10, Thread 3] Critical section done, previously next=0, now next=3
+[Iteration 10, Thread 2] Got lock
+[Iteration 10, Thread 2] Critical section done, previously next=3, now next=2
+[Iteration 10, Thread 1] Got lock
+[Iteration 10, Thread 1] Critical section done, previously next=2, now next=1
+Iteration 10 completed
+PASSED :-)
'''
from testlib import *
-cpu_types = ('DerivO3CPU', 'TimingSimpleCPU')
+cpu_types = (
+ # We're currently ignoring these cpu_types (therefore, disabling the test)
+ # due to a `fatal:syscall set_tid_address (#166)` fatal error being thrown.
+ # This is documented in this gem5 Jira ticket:
+ # https://gem5.atlassian.net/browse/GEM5-747
+ # 'DerivO3CPU',
+ # 'TimingSimpleCPU',
+)
if config.bin_path:
base_path = config.bin_path
'test_atomic', 'bin')
binary = 'test_atomic'
-url = config.resource_url + '/current/test-progs/pthread/bin/' + binary
-DownloadedProgram(url, base_path, binary)
+url = config.resource_url + '/test-progs/pthreads/sparc64/' + binary
+test_atomic = DownloadedProgram(url, base_path, binary)
verifiers = (
- verifier.MatchStdoutNoPerf(joinpath(getcwd(), 'ref/sparc/linux/simout')),
+ verifier.MatchStdoutNoPerf(joinpath(getcwd(), 'ref/sparc64/simout')),
)
for cpu in cpu_types:
gem5_verify_config(
name='test-atomic-' + cpu,
verifiers=verifiers,
+ fixtures=(test_atomic,),
config=joinpath(getcwd(), 'atomic_system.py'),
config_args=['--cpu-type', cpu,
'--num-cores', '8',
'--cmd', joinpath(base_path, binary)],
valid_isas=('SPARC',),
valid_hosts=constants.supported_hosts,
+ length = constants.long_tag,
)
projects / gem5.git / commitdiff