cpu/rocket: move csr to IO region

diff --git a/litex/soc/cores/cpu/rocket/core.py b/litex/soc/cores/cpu/rocket/core.py
index 4f46ae2b20854f1b81d1c3ee7540dab8d2c14450..54c31596c62be3db117f5377a18747a8dfc907e4 100644 (file)
--- a/litex/soc/cores/cpu/rocket/core.py
+++ b/litex/soc/cores/cpu/rocket/core.py
@@ -64,7 +64,7 @@ class RocketRV64(CPU):
         return {
             "rom"  : 0x10000000,
             "sram" : 0x11000000,
-            "csr"  : 0x12000000,
+            "csr"  : 0x92000000,
         }
 
     @property