add sv.setvl to instructions as a major hack

so that pack/unpack can be implemented
https://bugs.libre-soc.org/show_bug.cgi?id=871

diff --git a/openpower/isatables/RM-2P-1S1D.csv b/openpower/isatables/RM-2P-1S1D.csv
index 536ed0b68688c2d66bbc7b810041918d32872391..086a1e49af8b2e8888b6a7d74efc7c4dea48007e 100644 (file)
--- a/openpower/isatables/RM-2P-1S1D.csv
+++ b/openpower/isatables/RM-2P-1S1D.csv
@@ -28,6 +28,7 @@ xori,NORMAL,,2P,EXTRA3,d:RA,s:RS,0,0,RS,0,0,RA,0,0,0
 xoris,NORMAL,,2P,EXTRA3,d:RA,s:RS,0,0,RS,0,0,RA,0,0,0
 subfic,NORMAL,,2P,EXTRA3,d:RT,s:RA,0,0,RA,0,0,RT,0,0,0
 fishmv,NORMAL,,2P,EXTRA3,d:FRS,s:FRS,0,0,FRS,0,0,FRS,0,0,0
+setvl,NORMAL,,2P,EXTRA3,d:RT,s:RA,0,0,RA_OR_ZERO,0,0,RT_OR_ZERO,0,CR0,0
 cntlzw,NORMAL,,2P,EXTRA3,d:RA;d:CR0,s:RS,0,0,RS,0,0,RA,0,CR0,0
 cntlzd,NORMAL,,2P,EXTRA3,d:RA;d:CR0,s:RS,0,0,RS,0,0,RA,0,CR0,0
 subfze,NORMAL,,2P,EXTRA3,d:RT;d:CR0,s:RA,0,0,RA,0,0,RT,0,CR0,0

diff --git a/src/openpower/sv/sv_analysis.py b/src/openpower/sv/sv_analysis.py
index 1e91f5fac0e13e3116c44a89baea1277e4136dea..7f9e7a49557fe346b1409bd2041f2cbe005bd051 100644 (file)
--- a/src/openpower/sv/sv_analysis.py
+++ b/src/openpower/sv/sv_analysis.py
@@ -320,8 +320,6 @@ def read_csvs():
                 continue
             if 'addpcis' in insn_name: # skip for now
                 continue
-            if insn_name in ['setvl', ]:  # SVP64 opcodes
-                continue
 
             insns[(insn_name, condition)] = row  # accumulate csv data
             insn_to_csv[insn_name] = csvname_  # CSV file name by instruction
@@ -518,9 +516,12 @@ def extra_classifier(insn_name, value, name, res, regs):
             res['0'] = 'd:BI'  # BI: Rdest1_EXTRA3
             res['1'] = 's:BI'  # BI: Rsrc1_EXTRA3
         elif insn_name == 'fishmv':
-            # an overwrite ibstruction
+            # an overwrite instruction
             res['0'] = 'd:FRS'  # FRS: Rdest1_EXTRA3
             res['1'] = 's:FRS'  # FRS: Rsrc1_EXTRA3
+        elif insn_name == 'setvl':
+            res['0'] = 'd:RT'  # RT: Rdest1_EXTRA3
+            res['1'] = 's:RA'  # RS: Rsrc1_EXTRA3
         else:
             res['0'] = 'TODO'
             print("regs TODO", insn_name, regs)

diff --git a/src/openpower/sv/trans/test_pysvp64dis.py b/src/openpower/sv/trans/test_pysvp64dis.py
index a27274d884b1e398b2db66000dde6f1d3d38f3e9..8b68ecc122ea2097a2a2072ab70ecff930aacc08 100644 (file)
--- a/src/openpower/sv/trans/test_pysvp64dis.py
+++ b/src/openpower/sv/trans/test_pysvp64dis.py
@@ -77,6 +77,7 @@ class SVSTATETestCase(unittest.TestCase):
     def test_6_sv_setvl(self):
         expected = [
                     "sv.setvl 5,4,5,0,1,1",
+                    "sv.setvl 63,35,5,0,1,1",
                         ]
         self._do_tst(expected)