i386: Increase Skylake SImode pseudo register store cost

On Skylake, SImode store cost isn't less than half cost of 128-bit vector
store.  This patch increases Skylake SImode pseudo register store cost to
make it the same as QImode and HImode.

gcc/

	PR target/91446
	* config/i386/x86-tune-costs.h (skylake_cost): Increase SImode
	pseudo register store cost from 3 to 6 to make it the same as
	QImode and HImode.

gcc/testsuite/

	PR target/91446
	* gcc.target/i386/pr91446.c: New test.

From-SVN: r275905

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 6be55cd8adb17bd79744f2cee68ad9b6df8f68c2..d74b19f7109770bf1c05b96f8c965951efabb0b2 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,10 @@
+2019-09-18  H.J. Lu  <hongjiu.lu@intel.com>
+
+       PR target/91446
+       * config/i386/x86-tune-costs.h (skylake_cost): Increase SImode
+       pseudo register store cost from 3 to 6 to make it the same as
+       QImode and HImode.
+
 2019-09-18  Wilco Dijkstra  <wdijkstr@arm.com>
 
        * config/arm/arm.md (maddsidi4): Remove expander.

diff --git a/gcc/config/i386/x86-tune-costs.h b/gcc/config/i386/x86-tune-costs.h
index 00edece3eb68a215f7ea851a9826471b6d8c9cd1..42c9c2530c981218fc3ae6a8353b0cef217136b4 100644 (file)
--- a/gcc/config/i386/x86-tune-costs.h
+++ b/gcc/config/i386/x86-tune-costs.h
@@ -1638,7 +1638,7 @@ struct processor_costs skylake_cost = {
   {4, 4, 4},                           /* cost of loading integer registers
                                           in QImode, HImode and SImode.
                                           Relative to reg-reg move (2).  */
-  {6, 6, 3},                           /* cost of storing integer registers */
+  {6, 6, 6},                           /* cost of storing integer registers */
   {6, 6, 6, 10, 20},                   /* cost of loading SSE register
                                           in 32bit, 64bit, 128bit, 256bit and 512bit */
   {8, 8, 8, 12, 24},                   /* cost of storing SSE register

diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index dc84ed95055ffc019340e37c2e2a51374f862b50..8ea581d775e8818525082344da2dfcae09e276eb 100644 (file)
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,8 @@
+2019-09-18  H.J. Lu  <hongjiu.lu@intel.com>
+
+       PR target/91446
+       * gcc.target/i386/pr91446.c: New test.
+
 2019-09-18  Eric Botcazou  <ebotcazou@adacore.com>
 
        * gnat.dg/warn31.adb, gnat.dg/warn31.ads: New testcase.

diff --git a/gcc/testsuite/gcc.target/i386/pr91446.c b/gcc/testsuite/gcc.target/i386/pr91446.c
new file mode 100644 (file)
index 0000000..f7c4bea
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/pr91446.c
@@ -0,0 +1,24 @@
+/* { dg-do compile { target { ! ia32 } } } */
+/* { dg-options "-O2 -march=skylake -ftree-slp-vectorize -mtune-ctrl=^sse_typeless_stores" } */
+
+typedef struct
+{
+  unsigned long long width, height;
+  long long x, y;
+} info;
+
+extern void bar (info *);
+
+void
+foo (unsigned long long width, unsigned long long height,
+     long long x, long long y)
+{
+  info t;
+  t.width = width;
+  t.height = height;
+  t.x = x;
+  t.y = y;
+  bar (&t);
+}
+
+/* { dg-final { scan-assembler-times "vmovdqa\[^\n\r\]*xmm\[0-9\]" 2 } } */