cpu: add more instruction mix statistics

For the o3, add instruction mix (OpClass) histogram at commit (stats
also already collected at issue). For the simple CPUs we add a
histogram of executed instructions

diff --git a/src/cpu/o3/commit.hh b/src/cpu/o3/commit.hh
index cd663e2df6ad898062b3ebf6742af7992a7a23dd..ba594a2d2987ecbbab4cea684a21667e856d93d5 100644 (file)
--- a/src/cpu/o3/commit.hh
+++ b/src/cpu/o3/commit.hh
@@ -532,6 +532,8 @@ class DefaultCommit
     Stats::Vector statComInteger;
     /** Total number of function calls */
     Stats::Vector statComFunctionCalls;
+    /** Committed instructions by instruction type (OpClass) */
+    Stats::Vector2d statCommittedInstType;
 
     /** Number of cycles where the commit bandwidth limit is reached. */
     Stats::Scalar commitEligibleSamples;

diff --git a/src/cpu/o3/commit_impl.hh b/src/cpu/o3/commit_impl.hh
index 35d21d0715925f21e820a41d4a31fc6a22c1dac0..333687c848280a6191a1c940c5d672eab438e312 100644 (file)
--- a/src/cpu/o3/commit_impl.hh
+++ b/src/cpu/o3/commit_impl.hh
@@ -273,6 +273,14 @@ DefaultCommit<Impl>::regStats()
         .flags(total)
         ;
 
+    statCommittedInstType
+        .init(numThreads,Enums::Num_OpClass)
+        .name(name() + ".op_class")
+        .desc("Class of committed instruction")
+        .flags(total | pdf | dist)
+        ;
+    statCommittedInstType.ysubnames(Enums::OpClassStrings);
+
     commitEligible
         .init(cpu->numThreads)
         .name(name() + ".bw_limited")
@@ -1032,6 +1040,7 @@ DefaultCommit<Impl>::commitInsts()
 
             if (commit_success) {
                 ++num_committed;
+                statCommittedInstType[tid][head_inst->opClass()]++;
                 ppCommit->notify(head_inst);
 
                 changedROBNumEntries[tid] = true;

diff --git a/src/cpu/simple/base.cc b/src/cpu/simple/base.cc
index 3adf6d27f47e33a5a14d32e6f4982d63ee6a672a..f022d05e0c8964470f81bdaee4b71b27f413d058 100644 (file)
--- a/src/cpu/simple/base.cc
+++ b/src/cpu/simple/base.cc
@@ -286,6 +286,16 @@ BaseSimpleCPU::regStats()
         .prereq(dcacheRetryCycles)
         ;
 
+    statExecutedInstType
+        .init(Enums::Num_OpClass)
+        .name(name() + ".op_class")
+        .desc("Class of executed instruction")
+        .flags(total | pdf | dist)
+        ;
+    for (unsigned i = 0; i < Num_OpClasses; ++i) {
+        statExecutedInstType.subname(i, Enums::OpClassStrings[i]);
+    }
+
     idleFraction = constant(1.0) - notIdleFraction;
     numIdleCycles = idleFraction * numCycles;
     numBusyCycles = (notIdleFraction)*numCycles;
@@ -532,6 +542,8 @@ BaseSimpleCPU::postExecute()
     }
     /* End power model statistics */
 
+    statExecutedInstType[curStaticInst->opClass()]++;
+
     if (FullSystem)
         traceFunctions(instAddr);
 

diff --git a/src/cpu/simple/base.hh b/src/cpu/simple/base.hh
index ad672da6c4d05ab7bbb59e5422875dbed7797a26..47034c300c9555a554d31af72df073898f1a4268 100644 (file)
--- a/src/cpu/simple/base.hh
+++ b/src/cpu/simple/base.hh
@@ -283,6 +283,9 @@ class BaseSimpleCPU : public BaseCPU
     Stats::Scalar numBranchMispred;
     /// @}
 
+    // instruction mix histogram by OpClass
+    Stats::Vector statExecutedInstType;
+
     void serializeThread(std::ostream &os, ThreadID tid);
     void unserializeThread(Checkpoint *cp, const std::string &section,
                            ThreadID tid);