core: Implement mtmsr instruction

This is like mtmsrd except it only alters the lower 32 bits of the MSR.

Signed-off-by: Paul Mackerras <paulus@ozlabs.org>

diff --git a/decode1.vhdl b/decode1.vhdl
index 5d6a55777af2a4355e53b0e27a9a7104f3ff54d4..6624a53555f2261ff0a5904b862d99b80da6c14c 100644 (file)
--- a/decode1.vhdl
+++ b/decode1.vhdl
@@ -313,6 +313,7 @@ architecture behaviour of decode1 is
         2#1100001001#  =>       (ALU,    OP_MOD,       RA,         RB,          NONE, RT,   '0', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '0', '1', NONE, '0', '0'), -- modsd
         2#1100001011#  =>       (ALU,    OP_MOD,       RA,         RB,          NONE, RT,   '0', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '1', '1', NONE, '0', '0'), -- modsw
         2#0010010000#  =>       (ALU,    OP_MTCRF,     NONE,       NONE,        RS,   NONE, '0', '1', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '0', '0', NONE, '0', '0'), -- mtcrf/mtocrf
+        2#0010010010#  =>       (ALU,    OP_MTMSRD,    NONE,       NONE,        RS,   NONE, '0', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '1', '0', NONE, '0', '1'), -- mtmsr
         2#0010110010#  =>       (ALU,    OP_MTMSRD,    NONE,       NONE,        RS,   NONE, '0', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '0', '0', NONE, '0', '1'), -- mtmsrd # ignore top bits and d
         2#0111010011#  =>       (ALU,    OP_MTSPR,     NONE,       NONE,        RS,   SPR,  '0', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '0', '0', NONE, '0', '0'), -- mtspr
         2#0001001001#  =>       (ALU,    OP_MUL_H64,   RA,         RB,          NONE, RT,   '0', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '0', '1', RC,   '0', '0'), -- mulhd

diff --git a/execute1.vhdl b/execute1.vhdl
index b6387b9d5b3c8c339dd81dd6057892555f80ef5d..de6bd251c009dfce6e7dda4a5a341b3fb5a9a719 100644 (file)
--- a/execute1.vhdl
+++ b/execute1.vhdl
@@ -993,8 +993,11 @@ begin
                 else
                     -- Architecture says to leave out bits 3 (HV), 51 (ME)
                     -- and 63 (LE) (IBM bit numbering)
-                    ctrl_tmp.msr(63 downto 61) <= c_in(63 downto 61);
-                    ctrl_tmp.msr(59 downto 13) <= c_in(59 downto 13);
+                    if e_in.is_32bit = '0' then
+                        ctrl_tmp.msr(63 downto 61) <= c_in(63 downto 61);
+                        ctrl_tmp.msr(59 downto 32) <= c_in(59 downto 32);
+                    end if;
+                    ctrl_tmp.msr(31 downto 13) <= c_in(31 downto 13);
                     ctrl_tmp.msr(11 downto 1)  <= c_in(11 downto 1);
                     if c_in(MSR_PR) = '1' then
                         ctrl_tmp.msr(MSR_EE) <= '1';