cpu: add buses list and use it in soc_core to add bus masters

diff --git a/litex/soc/cores/cpu/minerva/core.py b/litex/soc/cores/cpu/minerva/core.py
index 3cda5a1957e3a915e036610759dbe0289d9fa421..8bc86829d383c6944dc69bdec43308dee5fd807e 100644 (file)
--- a/litex/soc/cores/cpu/minerva/core.py
+++ b/litex/soc/cores/cpu/minerva/core.py
@@ -34,6 +34,7 @@ class Minerva(CPU):
         self.reset     = Signal()
         self.ibus      = wishbone.Interface()
         self.dbus      = wishbone.Interface()
+        self.buses     = [self.ibus, self.dbus]
         self.interrupt = Signal(32)
 
         # # #

diff --git a/litex/soc/cores/cpu/mor1kx/core.py b/litex/soc/cores/cpu/mor1kx/core.py
index 16a43e89363e2c660bb9d9b13f5a54c77fc04240..954401bdc6949bf00fe5bfa0240c8054c4597580 100644 (file)
--- a/litex/soc/cores/cpu/mor1kx/core.py
+++ b/litex/soc/cores/cpu/mor1kx/core.py
@@ -63,11 +63,12 @@ class MOR1KX(CPU):
 
     def __init__(self, platform, variant="standard"):
         assert variant in CPU_VARIANTS, "Unsupported variant %s" % variant
-        self.platform = platform
-        self.variant  = variant
+        self.platform  = platform
+        self.variant   = variant
         self.reset     = Signal()
         self.ibus      = i = wishbone.Interface()
         self.dbus      = d = wishbone.Interface()
+        self.buses     = [i, d]
         self.interrupt = Signal(32)
 
         if variant == "linux":

diff --git a/litex/soc/cores/cpu/picorv32/core.py b/litex/soc/cores/cpu/picorv32/core.py
index c9b3af5fd03ddb415af0b6be1fac09c7707e005b..a190cb779f8a499129a50551230c6f1942e61634 100644 (file)
--- a/litex/soc/cores/cpu/picorv32/core.py
+++ b/litex/soc/cores/cpu/picorv32/core.py
@@ -60,6 +60,7 @@ class PicoRV32(CPU):
         self.reset     = Signal()
         self.ibus      = i = wishbone.Interface()
         self.dbus      = d = wishbone.Interface()
+        self.buses     = [i, d]
         self.interrupt = Signal(32)
         self.trap      = Signal()
 

diff --git a/litex/soc/cores/cpu/rocket/core.py b/litex/soc/cores/cpu/rocket/core.py
index c9fdb0ddc472f23ca2a5fc63834b37e86b23a5a3..3a7320c5f8f53d5a8a3487ab4621593ffe5093be 100644 (file)
--- a/litex/soc/cores/cpu/rocket/core.py
+++ b/litex/soc/cores/cpu/rocket/core.py
@@ -94,6 +94,8 @@ class RocketRV64(CPU):
         self.ibus = ibus = wishbone.Interface()
         self.dbus = dbus = wishbone.Interface()
 
+        self.buses = [ibus, dbus]
+
         # # #
 
         self.cpu_params = dict(

diff --git a/litex/soc/cores/cpu/vexriscv/core.py b/litex/soc/cores/cpu/vexriscv/core.py
index 375dd9a9e5c917c1c2c4a2720cb3edfa197efce7..2accda028898c4eb2db426058e5459b5ab698a31 100644 (file)
--- a/litex/soc/cores/cpu/vexriscv/core.py
+++ b/litex/soc/cores/cpu/vexriscv/core.py
@@ -102,10 +102,11 @@ class VexRiscv(CPU, AutoCSR):
         self.platform         = platform
         self.variant          = variant
         self.external_variant = None
-        self.reset     = Signal()
-        self.ibus      = ibus = wishbone.Interface()
-        self.dbus      = dbus = wishbone.Interface()
-        self.interrupt = Signal(32)
+        self.reset      = Signal()
+        self.ibus       = ibus = wishbone.Interface()
+        self.dbus       = dbus = wishbone.Interface()
+        self.buses      = [ibus, dbus]
+        self.interrupt  = Signal(32)
 
         self.cpu_params = dict(
                 i_clk=ClockSignal(),

diff --git a/litex/soc/integration/soc_core.py b/litex/soc/integration/soc_core.py
index 55278bbc47f0150d996fa59e0b53bb9463bfe1a8..0284252f2aba5042492c1c5851e5b30450bc4856 100644 (file)
--- a/litex/soc/integration/soc_core.py
+++ b/litex/soc/integration/soc_core.py
@@ -182,9 +182,9 @@ class SoCCore(Module):
             self.cpu.set_reset_address(self.soc_mem_map["rom"] if integrated_rom_size else cpu_reset_address)
             self.config["CPU_RESET_ADDR"] = self.cpu.reset_address
 
-            # Add Instruction/Data buses as Wisbone masters
-            self.add_wb_master(self.cpu.ibus)
-            self.add_wb_master(self.cpu.dbus)
+            # Add CPU buses as Wisbone masters
+            for bus in self.cpu.buses:
+                self.add_wb_master(bus)
 
             # Add CPU CSR (dynamic)
             self.add_csr("cpu", allow_user_defined=True)