Allow combination of rand and const modifiers

diff --git a/frontends/verilog/verilog_parser.y b/frontends/verilog/verilog_parser.y
index 2886db0e56a134963cfc2fa06d82c2a1f5b5cb03..8bd58d24c8cb0ec089c3a09ebdb6a0ecbf6655d7 100644 (file)
--- a/frontends/verilog/verilog_parser.y
+++ b/frontends/verilog/verilog_parser.y
@@ -651,8 +651,16 @@ wire_type_signedness:
        %empty;
 
 wire_type_const_rand:
-       TOK_CONST { current_wire_const = true; } |
-       TOK_RAND  { current_wire_rand = true;  } |
+       TOK_RAND TOK_CONST {
+           current_wire_rand = true;
+           current_wire_const = true;
+       } |
+       TOK_CONST {
+           current_wire_const = true;
+       } |
+       TOK_RAND {
+           current_wire_rand = true;
+       } |
        %empty;
 
 opt_wire_type_token:

diff --git a/tests/various/rand_const.sv b/tests/various/rand_const.sv
new file mode 100644 (file)
index 0000000..be00812
--- /dev/null
+++ b/tests/various/rand_const.sv
@@ -0,0 +1,8 @@
+module top;
+       rand const reg rx;
+       const reg ry;
+       rand reg rz;
+       rand const integer ix;
+       const integer iy;
+       rand integer iz;
+endmodule

diff --git a/tests/various/rand_const.ys b/tests/various/rand_const.ys
new file mode 100644 (file)
index 0000000..74e43c7
--- /dev/null
+++ b/tests/various/rand_const.ys
@@ -0,0 +1 @@
+read_verilog -sv rand_const.sv