return assigned;
bi_foreach_src(ins, s) {
- if (s == 0 && ins->type == BI_LOAD_VAR_ADDRESS) continue;
+ if (s == 0 && (ins->type == BI_LOAD_VAR_ADDRESS || ins->type == BI_LOAD_ATTR)) continue;
if (ins->src[s] & BIR_INDEX_CONSTANT) {
/* TODO: lo/hi matching? */
RETURN_PACKED(pack);
}
+static unsigned
+bi_pack_add_ld_attr(bi_clause *clause, bi_instruction *ins, struct bi_registers *regs)
+{
+ /* Only direct loads supported */
+ assert(ins->src[0] == BIR_INDEX_CONSTANT);
+
+ struct bifrost_ld_attr pack = {
+ .src0 = bi_get_src(ins, regs, 1, false),
+ .src1 = bi_get_src(ins, regs, 2, false),
+ .location = ins->constant.u64,
+ .channels = MALI_POSITIVE(bi_load32_components(ins)),
+ .type = bi_pack_ldst_type(ins->dest_type),
+ .op = BIFROST_ADD_OP_LD_ATTR
+ };
+
+ bi_write_data_register(clause, ins);
+ RETURN_PACKED(pack);
+}
+
static unsigned
bi_pack_add_st_vary(bi_clause *clause, bi_instruction *ins, struct bi_registers *regs)
{
case BI_ISUB:
case BI_LOAD:
return BIFROST_ADD_NOP;
+ case BI_LOAD_ATTR:
+ return bi_pack_add_ld_attr(clause, bundle.add, regs);
case BI_LOAD_UNIFORM:
return bi_pack_add_ld_ubo(clause, bundle.add, regs);
- case BI_LOAD_ATTR:
- return BIFROST_ADD_NOP;
case BI_LOAD_VAR:
return bi_pack_add_ld_vary(clause, bundle.add, regs);
case BI_LOAD_VAR_ADDRESS:
bi_schedule_barrier(ctx);
}
+static bi_instruction
+bi_load_with_r61(enum bi_class T, nir_intrinsic_instr *instr)
+{
+ bi_instruction ld = bi_load(T, instr);
+ ld.src[1] = BIR_INDEX_REGISTER | 61; /* TODO: RA */
+ ld.src[2] = BIR_INDEX_REGISTER | 62;
+ ld.src[3] = 0;
+ ld.src_types[1] = nir_type_uint32;
+ ld.src_types[2] = nir_type_uint32;
+ ld.src_types[3] = nir_intrinsic_type(instr);
+ return ld;
+}
+
static void
bi_emit_st_vary(bi_context *ctx, nir_intrinsic_instr *instr)
{
- bi_instruction address = bi_load(BI_LOAD_VAR_ADDRESS, instr);
- address.src[1] = BIR_INDEX_REGISTER | 61; /* TODO: RA */
- address.src[2] = BIR_INDEX_REGISTER | 62;
- address.src[3] = 0;
- address.src_types[1] = nir_type_uint32;
- address.src_types[2] = nir_type_uint32;
- address.src_types[3] = nir_intrinsic_type(instr);
+ bi_instruction address = bi_load_with_r61(BI_LOAD_VAR_ADDRESS, instr);
address.dest = bi_make_temp(ctx);
address.dest_type = nir_type_uint32;
address.writemask = (1 << 12) - 1;
if (ctx->stage == MESA_SHADER_FRAGMENT)
bi_emit_ld_vary(ctx, instr);
else if (ctx->stage == MESA_SHADER_VERTEX)
- bi_emit(ctx, bi_load(BI_LOAD_ATTR, instr));
+ bi_emit(ctx, bi_load_with_r61(BI_LOAD_ATTR, instr));
else {
unreachable("Unsupported shader stage");
}