Add Verilog source location information to `AST_POSEDGE` and `AST_NEGEDGE` nodes.

diff --git a/frontends/verilog/verilog_parser.y b/frontends/verilog/verilog_parser.y
index 7447ab8d553cdc52f0a2d355b2dd8ac1f5a707fc..f762f9025f414cbce74707959f92315b071fd8d9 100644 (file)
--- a/frontends/verilog/verilog_parser.y
+++ b/frontends/verilog/verilog_parser.y
@@ -1924,11 +1924,13 @@ always_events:
 always_event:
        TOK_POSEDGE expr {
                AstNode *node = new AstNode(AST_POSEDGE);
+               SET_AST_NODE_LOC(node, @1, @1);
                ast_stack.back()->children.push_back(node);
                node->children.push_back($2);
        } |
        TOK_NEGEDGE expr {
                AstNode *node = new AstNode(AST_NEGEDGE);
+               SET_AST_NODE_LOC(node, @1, @1);
                ast_stack.back()->children.push_back(node);
                node->children.push_back($2);
        } |