* config/arm/cortex-m4.md: Add a new bypass.

From-SVN: r198021

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 3ccbb0c1ea2202459cf228489b9fa80ce29c7a83..a2408e6e7dd3cc8cf69332535d0d98e0cc5e39fe 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,7 @@
+2013-04-17  Terry Guo  <terry.guo@arm.com>
+
+       * config/arm/cortex-m4.md: Add a new bypass.
+
 2013-04-16   Naveen H.S  <Naveen.Hurugalawadi@caviumnetworks.com>
 
        * config/aarch64/aarch64.md (*adds_<optab><mode>_multp2):

diff --git a/gcc/config/arm/cortex-m4.md b/gcc/config/arm/cortex-m4.md
index 187867bfebc27934cc8af2960e040396b53df43c..47b03644f73bd911043776d83472d39d2f542877 100644 (file)
--- a/gcc/config/arm/cortex-m4.md
+++ b/gcc/config/arm/cortex-m4.md
@@ -84,6 +84,10 @@
        (eq_attr "type" "store4"))
   "cortex_m4_ex*5")
 
+(define_bypass 1 "cortex_m4_load1"
+                 "cortex_m4_store1_1,cortex_m4_store1_2"
+                 "arm_no_early_store_addr_dep")
+
 ;; If the address of load or store depends on the result of the preceding
 ;; instruction, the latency is increased by one.