Ruby Cache: Add param for marking caches as instruction only

diff --git a/configs/ruby/MOESI_hammer.py b/configs/ruby/MOESI_hammer.py
index fb755ba552ec8c6601af9524bd5c8a58ef351f03..4cc377ec819b017f137350d417cc9faebe78e57c 100644 (file)
--- a/configs/ruby/MOESI_hammer.py
+++ b/configs/ruby/MOESI_hammer.py
@@ -88,7 +88,8 @@ def create_system(options, system, piobus, dma_devices, ruby_system):
         #
         l1i_cache = L1Cache(size = options.l1i_size,
                             assoc = options.l1i_assoc,
-                            start_index_bit = block_size_bits)
+                            start_index_bit = block_size_bits,
+                            is_icache = True)
         l1d_cache = L1Cache(size = options.l1d_size,
                             assoc = options.l1d_assoc,
                             start_index_bit = block_size_bits)

diff --git a/src/mem/ruby/system/Cache.py b/src/mem/ruby/system/Cache.py
index ab3ec4b2997a80c0075287eb7111cd2d054f094a..79ab9b07066ae48c8f66f6097f657db7b4f36de2 100644 (file)
--- a/src/mem/ruby/system/Cache.py
+++ b/src/mem/ruby/system/Cache.py
@@ -39,3 +39,4 @@ class RubyCache(SimObject):
     assoc = Param.Int("");
     replacement_policy = Param.String("PSEUDO_LRU", "");
     start_index_bit = Param.Int(6, "index start, default 6 for 64-byte line");
+    is_icache = Param.Bool(False, "is instruction only cache");

diff --git a/src/mem/ruby/system/CacheMemory.cc b/src/mem/ruby/system/CacheMemory.cc
index fbf303ed83e677f950090864d9229e6ac30b2755..1564128d3dff4b736b064529a0ac6f2d4c637394 100644 (file)
--- a/src/mem/ruby/system/CacheMemory.cc
+++ b/src/mem/ruby/system/CacheMemory.cc
@@ -55,6 +55,7 @@ CacheMemory::CacheMemory(const Params *p)
     m_policy = p->replacement_policy;
     m_profiler_ptr = new CacheProfiler(name());
     m_start_index_bit = p->start_index_bit;
+    m_is_instruction_only_cache = p->is_icache;
 }
 
 void