cores/cpu/vexriscv: fix wrong revert

diff --git a/litex/soc/cores/cpu/vexriscv/verilog b/litex/soc/cores/cpu/vexriscv/verilog
index d7bbc2c167f1a0886c446d3c305d0ed4388570be..ebe4064653bc143bf92a0ccdd1099173620fcbf5 160000 (submodule)
--- a/litex/soc/cores/cpu/vexriscv/verilog
+++ b/litex/soc/cores/cpu/vexriscv/verilog
@@ -1 +1 @@
-Subproject commit d7bbc2c167f1a0886c446d3c305d0ed4388570be
+Subproject commit ebe4064653bc143bf92a0ccdd1099173620fcbf5