boards/platforms/genesys2: add minimum HPC connectors to be able to test SATA, add...

diff --git a/litex/boards/platforms/genesys2.py b/litex/boards/platforms/genesys2.py
index 0a5fdf1549ed0484e2df309ab8e584514a91ceda..f5d5a25cca842e2d6f91e7e0f70b559ef1ec4c0b 100644 (file)
--- a/litex/boards/platforms/genesys2.py
+++ b/litex/boards/platforms/genesys2.py
@@ -89,12 +89,28 @@ _io = [
 ]
 
 
+_connectors = [
+    ("HPC", {
+        "DP0_C2M_P": "Y2",
+        "DP0_C2M_N": "Y1",
+        "DP0_M2C_P": "AA4",
+        "DP0_M2C_N": "AA3",
+        "GBTCLK0_M2C_P": "L8",
+        "GBTCLK0_M2C_N": "L7",
+        }
+    ),
+]
+
 class Platform(XilinxPlatform):
-    def __init__(self):
-        XilinxPlatform.__init__(self, "xc7k325t-ffg900-2", _io, toolchain="vivado")
+    def __init__(self, programmer="vivado"):
+        XilinxPlatform.__init__(self, "xc7k325t-ffg900-2", _io, _connectors, toolchain="vivado")
+        self.programmer = programmer
 
     def create_programmer(self):
-        return VivadoProgrammer()
+        if self.programmer == "vivado":
+            return VivadoProgrammer()
+        else:
+            raise ValueError("{} programmer is not supported".format(programmer))
 
     def do_finalize(self, fragment):
         XilinxPlatform.do_finalize(self, fragment)