fprintf(f, "end\n");
fprintf(f, "endtask\n\n");
- for (auto it = design->modules.begin(); it != design->modules.end(); it++)
+ for (auto it = design->modules_.begin(); it != design->modules_.end(); it++)
{
std::map<std::string, int> signal_in;
std::map<std::string, std::string> signal_const;
fprintf(f, "initial begin\n");
fprintf(f, "\t// $dumpfile(\"testbench.vcd\");\n");
fprintf(f, "\t// $dumpvars(0, testbench);\n");
- for (auto it = design->modules.begin(); it != design->modules.end(); it++)
+ for (auto it = design->modules_.begin(); it != design->modules_.end(); it++)
if (!it->second->get_bool_attribute("\\gentb_skip"))
fprintf(f, "\t%s;\n", idy(it->first, "test").c_str());
fprintf(f, "\t$finish;\n");
{
if (!config->gates_mode)
return "subckt";
- if (!design->modules.count(RTLIL::escape_id(cell_type)))
+ if (!design->modules_.count(RTLIL::escape_id(cell_type)))
return "gate";
- if (design->modules.at(RTLIL::escape_id(cell_type))->get_bool_attribute("\\blackbox"))
+ if (design->modules_.at(RTLIL::escape_id(cell_type))->get_bool_attribute("\\blackbox"))
return "gate";
return "subckt";
}
extra_args(f, filename, args, argidx);
if (top_module_name.empty())
- for (auto & mod_it:design->modules)
+ for (auto & mod_it:design->modules_)
if (mod_it.second->get_bool_attribute("\\top"))
top_module_name = mod_it.first;
std::vector<RTLIL::Module*> mod_list;
- for (auto module_it : design->modules)
+ for (auto module_it : design->modules_)
{
RTLIL::Module *module = module_it.second;
if (module->get_bool_attribute("\\blackbox"))
extra_args(f, filename, args, argidx);
if (top_module_name.empty())
- for (auto & mod_it:design->modules)
+ for (auto & mod_it:design->modules_)
if (mod_it.second->get_bool_attribute("\\top"))
top_module_name = mod_it.first;
std::vector<RTLIL::Module*> mod_list;
- for (auto module_it : design->modules)
+ for (auto module_it : design->modules_)
{
RTLIL::Module *module = module_it.second;
if (module->get_bool_attribute("\\blackbox"))
extra_args(f, filename, args, argidx);
if (top_module_name.empty())
- for (auto & mod_it:design->modules)
+ for (auto & mod_it:design->modules_)
if (mod_it.second->get_bool_attribute("\\top"))
top_module_name = mod_it.first;
- for (auto module_it : design->modules)
+ for (auto module_it : design->modules_)
{
RTLIL::Module *module = module_it.second;
if (module->get_bool_attribute("\\blackbox"))
for (auto cell_it : module->cells_)
{
RTLIL::Cell *cell = cell_it.second;
- if (!design->modules.count(cell->type) || design->modules.at(cell->type)->get_bool_attribute("\\blackbox")) {
+ if (!design->modules_.count(cell->type) || design->modules_.at(cell->type)->get_bool_attribute("\\blackbox")) {
lib_cell_ports[cell->type];
for (auto p : cell->connections()) {
if (p.second.size() > 1)
// extract module dependencies
std::map<RTLIL::Module*, std::set<RTLIL::Module*>> module_deps;
- for (auto &mod_it : design->modules) {
+ for (auto &mod_it : design->modules_) {
module_deps[mod_it.second] = std::set<RTLIL::Module*>();
for (auto &cell_it : mod_it.second->cells_)
- if (design->modules.count(cell_it.second->type) > 0)
- module_deps[mod_it.second].insert(design->modules.at(cell_it.second->type));
+ if (design->modules_.count(cell_it.second->type) > 0)
+ module_deps[mod_it.second].insert(design->modules_.at(cell_it.second->type));
}
// simple good-enough topological sort
if (!flag_m) {
int count_selected_mods = 0;
- for (auto it = design->modules.begin(); it != design->modules.end(); it++) {
+ for (auto it = design->modules_.begin(); it != design->modules_.end(); it++) {
if (design->selected_whole_module(it->first))
flag_m = true;
if (design->selected(it->second))
fprintf(f, "autoidx %d\n", RTLIL::autoidx);
}
- for (auto it = design->modules.begin(); it != design->modules.end(); it++) {
+ for (auto it = design->modules_.begin(); it != design->modules_.end(); it++) {
if (!only_selected || design->selected(it->second)) {
if (only_selected)
fprintf(f, "\n");
for (auto lib : libs)
ct.setup_design(lib);
- for (auto module_it : design->modules)
+ for (auto module_it : design->modules_)
{
RTLIL::Module *module = module_it.second;
SigMap sigmap(module);
std::vector<RTLIL::SigSpec> port_sigs;
- if (design->modules.count(cell->type) == 0)
+ if (design->modules_.count(cell->type) == 0)
{
log("Warning: no (blackbox) module for cell type `%s' (%s.%s) found! Guessing order of ports.\n",
RTLIL::id2cstr(cell->type), RTLIL::id2cstr(module->name), RTLIL::id2cstr(cell->name));
}
else
{
- RTLIL::Module *mod = design->modules.at(cell->type);
+ RTLIL::Module *mod = design->modules_.at(cell->type);
std::vector<RTLIL::Wire*> ports;
for (auto wire_it : mod->wires_) {
extra_args(f, filename, args, argidx);
if (top_module_name.empty())
- for (auto & mod_it:design->modules)
+ for (auto & mod_it:design->modules_)
if (mod_it.second->get_bool_attribute("\\top"))
top_module_name = mod_it.first;
fprintf(f, "* SPICE netlist generated by %s\n", yosys_version_str);
fprintf(f, "\n");
- for (auto module_it : design->modules)
+ for (auto module_it : design->modules_)
{
RTLIL::Module *module = module_it.second;
if (module->get_bool_attribute("\\blackbox"))
extra_args(f, filename, args, argidx);
fprintf(f, "/* Generated by %s */\n", yosys_version_str);
- for (auto it = design->modules.begin(); it != design->modules.end(); it++) {
+ for (auto it = design->modules_.begin(); it != design->modules_.end(); it++) {
if (it->second->get_bool_attribute("\\blackbox") != blackboxes)
continue;
if (selected && !design->selected_whole_module(it->first)) {
(*it)->str = (*it)->str.substr(1);
if (defer)
(*it)->str = "$abstract" + (*it)->str;
- if (design->modules.count((*it)->str)) {
+ if (design->modules_.count((*it)->str)) {
if (!ignore_redef)
log_error("Re-definition of module `%s' at %s:%d!\n",
(*it)->str.c_str(), (*it)->filename.c_str(), (*it)->linenum);
(*it)->str.c_str(), (*it)->filename.c_str(), (*it)->linenum);
continue;
}
- design->modules[(*it)->str] = process_module(*it, defer);
+ design->modules_[(*it)->str] = process_module(*it, defer);
}
}
modname = "$paramod" + stripped_name + para_info;
}
- if (design->modules.count(modname) == 0) {
+ if (design->modules_.count(modname) == 0) {
new_ast->str = modname;
- design->modules[modname] = process_module(new_ast, false);
- design->modules[modname]->check();
+ design->modules_[modname] = process_module(new_ast, false);
+ design->modules_[modname]->check();
} else {
log("Found cached RTLIL representation for module `%s'.\n", modname.c_str());
}
std::string cell_name = RTLIL::escape_id(cell->args.at(0));
- if (design->modules.count(cell_name)) {
+ if (design->modules_.count(cell_name)) {
if (flag_ignore_redef)
continue;
log_error("Duplicate definition of cell/module %s.\n", RTLIL::id2cstr(cell_name));
}
module->fixup_ports();
- design->modules[module->name] = module;
+ design->modules_[module->name] = module;
cell_count++;
skip_cell:;
}
if (cell_types.count(type) > 0)
return true;
for (auto design : designs)
- if (design->modules.count(type) > 0)
+ if (design->modules_.count(type) > 0)
return true;
return false;
}
{
if (cell_types.count(type) == 0) {
for (auto design : designs)
- if (design->modules.count(type) > 0) {
- if (design->modules.at(type)->wires_.count(port))
- return design->modules.at(type)->wires_.at(port)->port_output;
+ if (design->modules_.count(type) > 0) {
+ if (design->modules_.at(type)->wires_.count(port))
+ return design->modules_.at(type)->wires_.at(port)->port_output;
return false;
}
return false;
{
if (cell_types.count(type) == 0) {
for (auto design : designs)
- if (design->modules.count(type) > 0) {
- if (design->modules.at(type)->wires_.count(port))
- return design->modules.at(type)->wires_.at(port)->port_input;
+ if (design->modules_.count(type) > 0) {
+ if (design->modules_.at(type)->wires_.count(port))
+ return design->modules_.at(type)->wires_.at(port)->port_input;
return false;
}
return false;
if (design->selected_active_module.empty())
{
- for (auto &it : design->modules)
+ for (auto &it : design->modules_)
if (RTLIL::unescape_id(it.first).substr(0, len) == text)
obj_names.push_back(strdup(RTLIL::id2cstr(it.first.c_str())));
}
else
- if (design->modules.count(design->selected_active_module) > 0)
+ if (design->modules_.count(design->selected_active_module) > 0)
{
- RTLIL::Module *module = design->modules.at(design->selected_active_module);
+ RTLIL::Module *module = design->modules_.at(design->selected_active_module);
for (auto &it : module->wires_)
if (RTLIL::unescape_id(it.first).substr(0, len) == text)
del_list.clear();
for (auto mod_name : selected_modules) {
- if (design->modules.count(mod_name) == 0)
+ if (design->modules_.count(mod_name) == 0)
del_list.push_back(mod_name);
selected_members.erase(mod_name);
}
del_list.clear();
for (auto &it : selected_members)
- if (design->modules.count(it.first) == 0)
+ if (design->modules_.count(it.first) == 0)
del_list.push_back(it.first);
for (auto mod_name : del_list)
selected_members.erase(mod_name);
for (auto &it : selected_members) {
del_list.clear();
for (auto memb_name : it.second)
- if (design->modules[it.first]->count_id(memb_name) == 0)
+ if (design->modules_[it.first]->count_id(memb_name) == 0)
del_list.push_back(memb_name);
for (auto memb_name : del_list)
it.second.erase(memb_name);
for (auto &it : selected_members)
if (it.second.size() == 0)
del_list.push_back(it.first);
- else if (it.second.size() == design->modules[it.first]->wires_.size() + design->modules[it.first]->memories.size() +
- design->modules[it.first]->cells_.size() + design->modules[it.first]->processes.size())
+ else if (it.second.size() == design->modules_[it.first]->wires_.size() + design->modules_[it.first]->memories.size() +
+ design->modules_[it.first]->cells_.size() + design->modules_[it.first]->processes.size())
add_list.push_back(it.first);
for (auto mod_name : del_list)
selected_members.erase(mod_name);
selected_modules.insert(mod_name);
}
- if (selected_modules.size() == design->modules.size()) {
+ if (selected_modules.size() == design->modules_.size()) {
full_selection = true;
selected_modules.clear();
selected_members.clear();
RTLIL::Design::~Design()
{
- for (auto it = modules.begin(); it != modules.end(); it++)
+ for (auto it = modules_.begin(); it != modules_.end(); it++)
delete it->second;
}
void RTLIL::Design::check()
{
#ifndef NDEBUG
- for (auto &it : modules) {
+ for (auto &it : modules_) {
assert(it.first == it.second->name);
assert(it.first.size() > 0 && (it.first[0] == '\\' || it.first[0] == '$'));
it.second->check();
void RTLIL::Design::optimize()
{
- for (auto &it : modules)
+ for (auto &it : modules_)
it.second->optimize();
for (auto &it : selection_stack)
it.optimize(this);
struct RTLIL::Design
{
- std::map<RTLIL::IdString, RTLIL::Module*> modules;
+ std::map<RTLIL::IdString, RTLIL::Module*> modules_;
std::vector<RTLIL::Selection> selection_stack;
std::map<RTLIL::IdString, RTLIL::Selection> selection_vars;
// call find_stub_nets() for each module that is either
// selected as a whole or contains selected objects.
- for (auto &it : design->modules)
+ for (auto &it : design->modules_)
if (design->selected_module(it.first))
find_stub_nets(design, it.second, report_bits);
}
log(" %s\n", arg.c_str());
log("Modules in current design:\n");
- for (auto &mod : design->modules)
+ for (auto &mod : design->modules_)
log(" %s (%zd wires, %zd cells)\n", RTLIL::id2cstr(mod.first),
mod.second->wires_.size(), mod.second->cells_.size());
}
log("Name of this module: %s\n", RTLIL::id2cstr(module->name));
- if (design->modules.count(module->name) != 0)
+ if (design->modules_.count(module->name) != 0)
log_error("A module with the name %s already exists!\n",
RTLIL::id2cstr(module->name));
- design->modules[module->name] = module;
+ design->modules_[module->name] = module;
}
} Test1Pass;
if (design->selection_stack.back().empty())
log_cmd_error("This command can't operator on an empty selection!\n");
- RTLIL::Module *module = design->modules.at("\\test");
+ RTLIL::Module *module = design->modules_.at("\\test");
RTLIL::SigSpec a(module->wires_.at("\\a")), x(module->wires_.at("\\x")),
y(module->wires_.at("\\y"));
free(p);
log_header("Re-integrating ABC results.\n");
- RTLIL::Module *mapped_mod = mapped_design->modules["\\netlist"];
+ RTLIL::Module *mapped_mod = mapped_design->modules_["\\netlist"];
if (mapped_mod == NULL)
log_error("ABC output file does not contain a module `netlist'.\n");
for (auto &it : mapped_mod->wires_) {
if (!constr_file.empty() && liberty_file.empty())
log_cmd_error("Got -constr but no -liberty!\n");
- for (auto &mod_it : design->modules)
+ for (auto &mod_it : design->modules_)
if (design->selected(mod_it.second)) {
if (mod_it.second->processes.size() > 0)
log("Skipping module %s as it contains processes.\n", mod_it.second->name.c_str());
int port_count = 0;
module->name = "\\netlist";
- design->modules[module->name] = module;
+ design->modules_[module->name] = module;
size_t buffer_size = 4096;
char *buffer = (char*)malloc(buffer_size);
for (auto &it : module->cells_)
{
- if (design->modules.count(it.second->type) == 0)
+ if (design->modules_.count(it.second->type) == 0)
continue;
- RTLIL::Module *mod = design->modules.at(it.second->type);
+ RTLIL::Module *mod = design->modules_.at(it.second->type);
if (!design->selected_whole_module(mod->name))
continue;
if (mod->get_bool_attribute("\\blackbox"))
}
extra_args(args, argidx, design);
- for (auto &mod : design->modules)
+ for (auto &mod : design->modules_)
{
RTLIL::Module *module = mod.second;
if (!design->selected_whole_module(module->name))
virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
{
RTLIL::Module *module = NULL;
- for (auto &it : design->modules) {
+ for (auto &it : design->modules_) {
if (!design->selected(it.second))
continue;
if (module != NULL)
log_header("Executing CONNWRAPPERS pass (connect extended ports of wrapper cells).\n");
- for (auto &mod_it : design->modules)
+ for (auto &mod_it : design->modules_)
if (design->selected(mod_it.second))
worker.work(design, mod_it.second);
}
std::string src_name = RTLIL::escape_id(args[1]);
std::string trg_name = RTLIL::escape_id(args[2]);
- if (design->modules.count(src_name) == 0)
+ if (design->modules_.count(src_name) == 0)
log_cmd_error("Can't find source module %s.\n", src_name.c_str());
- if (design->modules.count(trg_name) != 0)
+ if (design->modules_.count(trg_name) != 0)
log_cmd_error("Target module name %s already exists.\n", trg_name.c_str());
- design->modules[trg_name] = design->modules.at(src_name)->clone();
- design->modules[trg_name]->name = trg_name;
+ design->modules_[trg_name] = design->modules_.at(src_name)->clone();
+ design->modules_[trg_name]->name = trg_name;
}
} CopyPass;
std::vector<std::string> delete_mods;
- for (auto &mod_it : design->modules)
+ for (auto &mod_it : design->modules_)
{
if (design->selected_whole_module(mod_it.first) && !flag_input && !flag_output) {
delete_mods.push_back(mod_it.first);
}
for (auto &it : delete_mods) {
- delete design->modules.at(it);
- design->modules.erase(it);
+ delete design->modules_.at(it);
+ design->modules_.erase(it);
}
}
} DeletePass;
argidx = args.size();
}
- for (auto &it : copy_from_design->modules) {
+ for (auto &it : copy_from_design->modules_) {
if (sel.selected_whole_module(it.first)) {
copy_src_modules.push_back(it.second);
continue;
{
std::string trg_name = as_name.empty() ? mod->name : RTLIL::escape_id(as_name);
- if (copy_to_design->modules.count(trg_name))
- delete copy_to_design->modules.at(trg_name);
- copy_to_design->modules[trg_name] = mod->clone();
- copy_to_design->modules[trg_name]->name = trg_name;
+ if (copy_to_design->modules_.count(trg_name))
+ delete copy_to_design->modules_.at(trg_name);
+ copy_to_design->modules_[trg_name] = mod->clone();
+ copy_to_design->modules_[trg_name]->name = trg_name;
}
}
{
RTLIL::Design *design_copy = new RTLIL::Design;
- for (auto &it : design->modules)
- design_copy->modules[it.first] = it.second->clone();
+ for (auto &it : design->modules_)
+ design_copy->modules_[it.first] = it.second->clone();
design_copy->selection_stack = design->selection_stack;
design_copy->selection_vars = design->selection_vars;
if (reset_mode || !load_name.empty() || push_mode || pop_mode)
{
- for (auto &it : design->modules)
+ for (auto &it : design->modules_)
delete it.second;
- design->modules.clear();
+ design->modules_.clear();
design->selection_stack.clear();
design->selection_vars.clear();
if (pop_mode)
pushed_designs.pop_back();
- for (auto &it : saved_design->modules)
- design->modules[it.first] = it.second->clone();
+ for (auto &it : saved_design->modules_)
+ design->modules_[it.first] = it.second->clone();
design->selection_stack = saved_design->selection_stack;
design->selection_vars = saved_design->selection_vars;
{
extra_args(args, argidx, design);
- for (auto &mod : design->modules)
+ for (auto &mod : design->modules_)
{
int counter = 0;
{
extra_args(args, argidx, design);
- for (auto &mod : design->modules)
+ for (auto &mod : design->modules_)
{
RTLIL::Module *module = mod.second;
if (!design->selected(module))
if (!design->selected_active_module.empty())
{
- if (design->modules.count(design->selected_active_module) > 0)
- rename_in_module(design->modules.at(design->selected_active_module), from_name, to_name);
+ if (design->modules_.count(design->selected_active_module) > 0)
+ rename_in_module(design->modules_.at(design->selected_active_module), from_name, to_name);
}
else
{
- for (auto &mod : design->modules) {
+ for (auto &mod : design->modules_) {
if (mod.first == from_name || RTLIL::unescape_id(mod.first) == from_name) {
to_name = RTLIL::escape_id(to_name);
log("Renaming module %s to %s.\n", mod.first.c_str(), to_name.c_str());
RTLIL::Module *module = mod.second;
- design->modules.erase(module->name);
+ design->modules_.erase(module->name);
module->name = to_name;
- design->modules[module->name] = module;
+ design->modules_[module->name] = module;
goto rename_ok;
}
}
CellTypes ct(design);
extra_args(args, 1, design);
- for (auto &mod_it : design->modules)
+ for (auto &mod_it : design->modules_)
{
if (!design->selected(mod_it.second))
continue;
RTLIL::Selection newSelection(false);
- for (auto &mod_it : design->modules)
+ for (auto &mod_it : design->modules_)
if (design->selected(mod_it.second))
{
SccWorker worker(design, mod_it.second, allCellTypes, maxDepth);
RTLIL::Selection new_sel(false);
- for (auto &mod_it : design->modules)
+ for (auto &mod_it : design->modules_)
{
if (lhs.selected_whole_module(mod_it.first))
continue;
static void select_op_submod(RTLIL::Design *design, RTLIL::Selection &lhs)
{
- for (auto &mod_it : design->modules)
+ for (auto &mod_it : design->modules_)
{
if (lhs.selected_whole_module(mod_it.first))
{
for (auto &cell_it : mod_it.second->cells_)
{
- if (design->modules.count(cell_it.second->type) == 0)
+ if (design->modules_.count(cell_it.second->type) == 0)
continue;
lhs.selected_modules.insert(cell_it.second->type);
}
static void select_op_alias(RTLIL::Design *design, RTLIL::Selection &lhs)
{
- for (auto &mod_it : design->modules)
+ for (auto &mod_it : design->modules_)
{
if (lhs.selected_whole_module(mod_it.first))
continue;
if (!rhs.full_selection && rhs.selected_modules.size() == 0 && rhs.selected_members.size() == 0)
return;
lhs.full_selection = false;
- for (auto &it : design->modules)
+ for (auto &it : design->modules_)
lhs.selected_modules.insert(it.first);
}
for (auto &it : rhs.selected_members)
{
- if (design->modules.count(it.first) == 0)
+ if (design->modules_.count(it.first) == 0)
continue;
- RTLIL::Module *mod = design->modules[it.first];
+ RTLIL::Module *mod = design->modules_[it.first];
if (lhs.selected_modules.count(mod->name) > 0)
{
if (lhs.full_selection) {
lhs.full_selection = false;
- for (auto &it : design->modules)
+ for (auto &it : design->modules_)
lhs.selected_modules.insert(it.first);
}
{
int sel_objects = 0;
bool is_input, is_output;
- for (auto &mod_it : design->modules)
+ for (auto &mod_it : design->modules_)
{
if (lhs.selected_whole_module(mod_it.first) || !lhs.selected_module(mod_it.first))
continue;
}
sel.full_selection = false;
- for (auto &mod_it : design->modules)
+ for (auto &mod_it : design->modules_)
{
if (arg_mod.substr(0, 2) == "A:") {
if (!match_attr(mod_it.second->attributes, arg_mod.substr(2)))
}
if (arg == "-module" && argidx+1 < args.size()) {
RTLIL::IdString mod_name = RTLIL::escape_id(args[++argidx]);
- if (design->modules.count(mod_name) == 0)
+ if (design->modules_.count(mod_name) == 0)
log_cmd_error("No such module: %s\n", id2cstr(mod_name));
design->selected_active_module = mod_name;
got_module = true;
if (work_stack.size() > 0)
sel = &work_stack.back();
sel->optimize(design);
- for (auto mod_it : design->modules)
+ for (auto mod_it : design->modules_)
{
if (sel->selected_whole_module(mod_it.first) && list_mode)
log("%s\n", id2cstr(mod_it.first));
log_cmd_error("No selection to check.\n");
RTLIL::Selection *sel = &work_stack.back();
sel->optimize(design);
- for (auto mod_it : design->modules)
+ for (auto mod_it : design->modules_)
if (sel->selected_module(mod_it.first)) {
for (auto &it : mod_it.second->wires_)
if (sel->selected_member(mod_it.first, it.first))
std::string modname = RTLIL::escape_id(args[1]);
- if (design->modules.count(modname) == 0 && !design->selected_active_module.empty()) {
+ if (design->modules_.count(modname) == 0 && !design->selected_active_module.empty()) {
RTLIL::Module *module = NULL;
- if (design->modules.count(design->selected_active_module) > 0)
- module = design->modules.at(design->selected_active_module);
+ if (design->modules_.count(design->selected_active_module) > 0)
+ module = design->modules_.at(design->selected_active_module);
if (module != NULL && module->cells_.count(modname) > 0)
modname = module->cells_.at(modname)->type;
}
- if (design->modules.count(modname) > 0) {
+ if (design->modules_.count(modname) > 0) {
design->selected_active_module = modname;
design->selection_stack.back() = RTLIL::Selection();
select_filter_active_mod(design, design->selection_stack.back());
if (design->selected_active_module.empty())
{
- counter += log_matches("modules", pattern, design->modules);
+ counter += log_matches("modules", pattern, design->modules_);
}
else
- if (design->modules.count(design->selected_active_module) > 0)
+ if (design->modules_.count(design->selected_active_module) > 0)
{
- RTLIL::Module *module = design->modules.at(design->selected_active_module);
+ RTLIL::Module *module = design->modules_.at(design->selected_active_module);
counter += log_matches("wires", pattern, module->wires_);
counter += log_matches("memories", pattern, module->memories);
counter += log_matches("cells", pattern, module->cells_);
}
extra_args(args, argidx, design);
- for (auto &mod : design->modules)
+ for (auto &mod : design->modules_)
{
RTLIL::Module *module = mod.second;
}
extra_args(args, argidx, design);
- for (auto &mod : design->modules)
+ for (auto &mod : design->modules_)
{
RTLIL::Module *module = mod.second;
if (!got_value)
log_cmd_error("One of the options -zero, -one, or -random <seed> must be specified.\n");
- for (auto &mod_it : design->modules)
+ for (auto &mod_it : design->modules_)
{
RTLIL::Module *module = mod_it.second;
if (!design->selected(module))
design->optimize();
page_counter = 0;
- for (auto &mod_it : design->modules)
+ for (auto &mod_it : design->modules_)
{
module = mod_it.second;
if (!design->selected_module(module->name))
if (format != "ps") {
int modcount = 0;
- for (auto &mod_it : design->modules) {
+ for (auto &mod_it : design->modules_) {
if (mod_it.second->get_bool_attribute("\\blackbox"))
continue;
if (mod_it.second->cells_.empty() && mod_it.second->connections().empty())
log_header("Executing SPLICE pass (creating cells for signal splicing).\n");
- for (auto &mod_it : design->modules)
+ for (auto &mod_it : design->modules_)
{
if (!design->selected(mod_it.second))
continue;
}
extra_args(args, argidx, design);
- for (auto &mod_it : design->modules)
+ for (auto &mod_it : design->modules_)
{
RTLIL::Module *module = mod_it.second;
if (!design->selected(module))
for (argidx = 1; argidx < args.size(); argidx++)
{
if (args[argidx] == "-top" && argidx+1 < args.size()) {
- if (design->modules.count(RTLIL::escape_id(args[argidx+1])) == 0)
+ if (design->modules_.count(RTLIL::escape_id(args[argidx+1])) == 0)
log_cmd_error("Can't find module %s.\n", args[argidx+1].c_str());
- top_mod = design->modules.at(RTLIL::escape_id(args[++argidx]));
+ top_mod = design->modules_.at(RTLIL::escape_id(args[++argidx]));
continue;
}
break;
}
extra_args(args, argidx, design);
- for (auto &it : design->modules)
+ for (auto &it : design->modules_)
{
if (!design->selected_module(it.first))
continue;
ct.setup_stdcells();
ct.setup_stdcells_mem();
- for (auto &mod_it : design->modules)
+ for (auto &mod_it : design->modules_)
{
if (!design->selected(mod_it.second))
continue;
log_header("Executing FSM_EXPAND pass (merging auxiliary logic into FSMs).\n");
extra_args(args, 1, design);
- for (auto &mod_it : design->modules) {
+ for (auto &mod_it : design->modules_) {
if (!design->selected(mod_it.second))
continue;
std::vector<RTLIL::Cell*> fsm_cells;
}
extra_args(args, argidx, design);
- for (auto &mod_it : design->modules)
+ for (auto &mod_it : design->modules_)
if (design->selected(mod_it.second))
for (auto &cell_it : mod_it.second->cells_)
if (cell_it.second->type == "$fsm" && design->selected(mod_it.second, cell_it.second)) {
ct.setup_stdcells();
ct.setup_stdcells_mem();
- for (auto &mod_it : design->modules)
+ for (auto &mod_it : design->modules_)
{
if (!design->selected(mod_it.second))
continue;
log_header("Executing FSM_INFO pass (dumping all available information on FSM cells).\n");
extra_args(args, 1, design);
- for (auto &mod_it : design->modules)
+ for (auto &mod_it : design->modules_)
if (design->selected(mod_it.second))
for (auto &cell_it : mod_it.second->cells_)
if (cell_it.second->type == "$fsm" && design->selected(mod_it.second, cell_it.second)) {
log_header("Executing FSM_MAP pass (mapping FSMs to basic logic).\n");
extra_args(args, 1, design);
- for (auto &mod_it : design->modules) {
+ for (auto &mod_it : design->modules_) {
if (!design->selected(mod_it.second))
continue;
std::vector<RTLIL::Cell*> fsm_cells;
log_header("Executing FSM_OPT pass (simple optimizations of FSMs).\n");
extra_args(args, 1, design);
- for (auto &mod_it : design->modules) {
+ for (auto &mod_it : design->modules_) {
if (design->selected(mod_it.second))
for (auto &cell_it : mod_it.second->cells_)
if (cell_it.second->type == "$fsm" and design->selected(mod_it.second, cell_it.second))
}
extra_args(args, argidx, design);
- for (auto &mod_it : design->modules)
+ for (auto &mod_it : design->modules_)
if (design->selected(mod_it.second))
for (auto &cell_it : mod_it.second->cells_)
if (cell_it.second->type == "$fsm" && design->selected(mod_it.second, cell_it.second))
{
std::set<std::string> found_celltypes;
- for (auto i1 : design->modules)
+ for (auto i1 : design->modules_)
for (auto i2 : i1.second->cells_)
{
RTLIL::Cell *cell = i2.second;
- if (cell->type[0] == '$' || design->modules.count(cell->type) > 0)
+ if (cell->type[0] == '$' || design->modules_.count(cell->type) > 0)
continue;
for (auto &pattern : celltypes)
if (!fnmatch(pattern.c_str(), RTLIL::unescape_id(cell->type).c_str(), FNM_NOESCAPE))
std::map<std::string, int> portwidths;
log("Generate module for cell type %s:\n", celltype.c_str());
- for (auto i1 : design->modules)
+ for (auto i1 : design->modules_)
for (auto i2 : i1.second->cells_)
if (i2.second->type == celltype) {
for (auto &conn : i2.second->connections()) {
RTLIL::Module *mod = new RTLIL::Module;
mod->name = celltype;
mod->attributes["\\blackbox"] = RTLIL::Const(1);
- design->modules[mod->name] = mod;
+ design->modules_[mod->name] = mod;
for (auto &decl : ports) {
RTLIL::Wire *wire = mod->addWire(decl.portname, portwidths.at(decl.portname));
cell->type = cell->type.substr(pos_type + 1);
}
- if (design->modules.count(cell->type) == 0)
+ if (design->modules_.count(cell->type) == 0)
{
- if (design->modules.count("$abstract" + cell->type))
+ if (design->modules_.count("$abstract" + cell->type))
{
- cell->type = design->modules.at("$abstract" + cell->type)->derive(design, cell->parameters);
+ cell->type = design->modules_.at("$abstract" + cell->type)->derive(design, cell->parameters);
cell->parameters.clear();
did_something = true;
continue;
continue;
loaded_module:
- if (design->modules.count(cell->type) == 0)
+ if (design->modules_.count(cell->type) == 0)
log_error("File `%s' from libdir does not declare module `%s'.\n", filename.c_str(), cell->type.c_str());
did_something = true;
}
if (cell->parameters.size() == 0)
continue;
- if (design->modules.at(cell->type)->get_bool_attribute("\\blackbox"))
+ if (design->modules_.at(cell->type)->get_bool_attribute("\\blackbox"))
continue;
- RTLIL::Module *mod = design->modules[cell->type];
+ RTLIL::Module *mod = design->modules_[cell->type];
cell->type = mod->derive(design, cell->parameters);
cell->parameters.clear();
did_something = true;
RTLIL::Cell *cell = it.first;
int idx = it.second.first, num = it.second.second;
- if (design->modules.count(cell->type) == 0)
+ if (design->modules_.count(cell->type) == 0)
log_error("Array cell `%s.%s' of unkown type `%s'.\n", RTLIL::id2cstr(module->name), RTLIL::id2cstr(cell->name), RTLIL::id2cstr(cell->type));
- RTLIL::Module *mod = design->modules[cell->type];
+ RTLIL::Module *mod = design->modules_[cell->type];
for (auto &conn : cell->connections_) {
int conn_size = conn.second.size();
used.insert(mod);
for (auto &it : mod->cells_) {
- if (design->modules.count(it.second->type) > 0)
- hierarchy_worker(design, used, design->modules[it.second->type], indent+4);
+ if (design->modules_.count(it.second->type) > 0)
+ hierarchy_worker(design, used, design->modules_[it.second->type], indent+4);
}
}
hierarchy_worker(design, used, top, 0);
std::vector<RTLIL::Module*> del_modules;
- for (auto &it : design->modules)
+ for (auto &it : design->modules_)
if (used.count(it.second) == 0)
del_modules.push_back(it.second);
if (!purge_lib && mod->get_bool_attribute("\\blackbox"))
continue;
log("Removing unused module `%s'.\n", mod->name.c_str());
- design->modules.erase(mod->name);
+ design->modules_.erase(mod->name);
delete mod;
}
if (args[argidx] == "-top") {
if (++argidx >= args.size())
log_cmd_error("Option -top requires an additional argument!\n");
- top_mod = design->modules.count(RTLIL::escape_id(args[argidx])) ? design->modules.at(RTLIL::escape_id(args[argidx])) : NULL;
- if (top_mod == NULL && design->modules.count("$abstract" + RTLIL::escape_id(args[argidx]))) {
+ top_mod = design->modules_.count(RTLIL::escape_id(args[argidx])) ? design->modules_.at(RTLIL::escape_id(args[argidx])) : NULL;
+ if (top_mod == NULL && design->modules_.count("$abstract" + RTLIL::escape_id(args[argidx]))) {
std::map<RTLIL::IdString, RTLIL::Const> empty_parameters;
- design->modules.at("$abstract" + RTLIL::escape_id(args[argidx]))->derive(design, empty_parameters);
- top_mod = design->modules.count(RTLIL::escape_id(args[argidx])) ? design->modules.at(RTLIL::escape_id(args[argidx])) : NULL;
+ design->modules_.at("$abstract" + RTLIL::escape_id(args[argidx]))->derive(design, empty_parameters);
+ top_mod = design->modules_.count(RTLIL::escape_id(args[argidx])) ? design->modules_.at(RTLIL::escape_id(args[argidx])) : NULL;
}
if (top_mod == NULL)
log_cmd_error("Module `%s' not found!\n", args[argidx].c_str());
log_push();
if (top_mod == NULL)
- for (auto &mod_it : design->modules)
+ for (auto &mod_it : design->modules_)
if (mod_it.second->get_bool_attribute("\\top"))
top_mod = mod_it.second;
while (did_something) {
did_something = false;
std::vector<std::string> modnames;
- modnames.reserve(design->modules.size());
- for (auto &mod_it : design->modules)
+ modnames.reserve(design->modules_.size());
+ for (auto &mod_it : design->modules_)
modnames.push_back(mod_it.first);
for (auto &modname : modnames) {
- if (design->modules.count(modname) == 0)
+ if (design->modules_.count(modname) == 0)
continue;
- if (expand_module(design, design->modules[modname], flag_check, libdirs))
+ if (expand_module(design, design->modules_[modname], flag_check, libdirs))
did_something = true;
}
if (did_something)
}
if (top_mod != NULL) {
- for (auto &mod_it : design->modules)
+ for (auto &mod_it : design->modules_)
if (mod_it.second == top_mod)
mod_it.second->attributes["\\top"] = RTLIL::Const(1);
else
std::map<std::pair<RTLIL::Module*,int>, RTLIL::IdString> pos_map;
std::vector<std::pair<RTLIL::Module*,RTLIL::Cell*>> pos_work;
- for (auto &mod_it : design->modules)
+ for (auto &mod_it : design->modules_)
for (auto &cell_it : mod_it.second->cells_) {
RTLIL::Cell *cell = cell_it.second;
- if (design->modules.count(cell->type) == 0)
+ if (design->modules_.count(cell->type) == 0)
continue;
for (auto &conn : cell->connections())
if (conn.first[0] == '$' && '0' <= conn.first[1] && conn.first[1] <= '9') {
- pos_mods.insert(design->modules.at(cell->type));
+ pos_mods.insert(design->modules_.at(cell->type));
pos_work.push_back(std::pair<RTLIL::Module*,RTLIL::Cell*>(mod_it.second, cell));
break;
}
for (auto &conn : cell->connections())
if (conn.first[0] == '$' && '0' <= conn.first[1] && conn.first[1] <= '9') {
int id = atoi(conn.first.c_str()+1);
- std::pair<RTLIL::Module*,int> key(design->modules.at(cell->type), id);
+ std::pair<RTLIL::Module*,int> key(design->modules_.at(cell->type), id);
if (pos_map.count(key) == 0) {
log(" Failed to map positional argument %d of cell %s.%s (%s).\n",
id, RTLIL::id2cstr(module->name), RTLIL::id2cstr(cell->name), RTLIL::id2cstr(cell->type));
RTLIL::Module *new_mod = new RTLIL::Module;
new_mod->name = submod.full_name;
- design->modules[new_mod->name] = new_mod;
+ design->modules_[new_mod->name] = new_mod;
int port_counter = 1, auto_name_counter = 1;
std::set<std::string> all_wire_names;
if (submodules.count(submod_str) == 0) {
submodules[submod_str].name = submod_str;
submodules[submod_str].full_name = module->name + "_" + submod_str;
- while (design->modules.count(submodules[submod_str].full_name) != 0 ||
+ while (design->modules_.count(submodules[submod_str].full_name) != 0 ||
module->count_id(submodules[submod_str].full_name) != 0)
submodules[submod_str].full_name += "_";
}
while (did_something) {
did_something = false;
std::vector<std::string> queued_modules;
- for (auto &mod_it : design->modules)
+ for (auto &mod_it : design->modules_)
if (handled_modules.count(mod_it.first) == 0 && design->selected_whole_module(mod_it.first))
queued_modules.push_back(mod_it.first);
for (auto &modname : queued_modules)
- if (design->modules.count(modname) != 0) {
- SubmodWorker worker(design, design->modules[modname]);
+ if (design->modules_.count(modname) != 0) {
+ SubmodWorker worker(design, design->modules_[modname]);
handled_modules.insert(modname);
did_something = true;
}
else
{
RTLIL::Module *module = NULL;
- for (auto &mod_it : design->modules) {
+ for (auto &mod_it : design->modules_) {
if (!design->selected_module(mod_it.first))
continue;
if (module != NULL)
virtual void execute(std::vector<std::string> args, RTLIL::Design *design) {
log_header("Executing MEMORY_COLLECT pass (generating $mem cells).\n");
extra_args(args, 1, design);
- for (auto &mod_it : design->modules)
+ for (auto &mod_it : design->modules_)
if (design->selected(mod_it.second))
handle_module(design, mod_it.second);
}
}
extra_args(args, argidx, design);
- for (auto &mod_it : design->modules)
+ for (auto &mod_it : design->modules_)
if (design->selected(mod_it.second))
handle_module(design, mod_it.second, flag_wr_only);
}
virtual void execute(std::vector<std::string> args, RTLIL::Design *design) {
log_header("Executing MEMORY_MAP pass (converting $mem cells to logic and flip-flops).\n");
extra_args(args, 1, design);
- for (auto &mod_it : design->modules)
+ for (auto &mod_it : design->modules_)
if (design->selected(mod_it.second))
handle_module(design, mod_it.second);
}
virtual void execute(std::vector<std::string> args, RTLIL::Design *design) {
log_header("Executing MEMORY_SHARE pass (consolidating $memrc/$memwr cells).\n");
extra_args(args, 1, design);
- for (auto &mod_it : design->modules)
+ for (auto &mod_it : design->modules_)
if (design->selected(mod_it.second))
MemoryShareWorker(design, mod_it.second);
}
virtual void execute(std::vector<std::string> args, RTLIL::Design *design) {
log_header("Executing MEMORY_UNPACK pass (generating $memrd/$memwr cells form $mem cells).\n");
extra_args(args, 1, design);
- for (auto &mod_it : design->modules)
+ for (auto &mod_it : design->modules_)
if (design->selected(mod_it.second))
handle_module(design, mod_it.second);
}
ct_reg.setup_internals_mem();
ct_reg.setup_stdcells_mem();
- for (auto &mod_it : design->modules) {
+ for (auto &mod_it : design->modules_) {
if (!design->selected_whole_module(mod_it.first)) {
if (design->selected(mod_it.second))
log("Skipping module %s as it is only partially selected.\n", id2cstr(mod_it.second->name));
count_rm_cells = 0;
count_rm_wires = 0;
- for (auto &mod_it : design->modules) {
+ for (auto &mod_it : design->modules_) {
if (design->selected_whole_module(mod_it.first) && mod_it.second->processes.size() == 0)
do {
OPT_DID_SOMETHING = false;
}
extra_args(args, argidx, design);
- for (auto &mod_it : design->modules)
+ for (auto &mod_it : design->modules_)
{
if (undriven)
replace_undriven(design, mod_it.second);
extra_args(args, 1, design);
int total_count = 0;
- for (auto &mod_it : design->modules) {
+ for (auto &mod_it : design->modules_) {
if (!design->selected_whole_module(mod_it.first)) {
if (design->selected(mod_it.second))
log("Skipping module %s as it is only partially selected.\n", id2cstr(mod_it.second->name));
extra_args(args, argidx, design);
int total_count = 0;
- for (auto &mod_it : design->modules) {
+ for (auto &mod_it : design->modules_) {
if (!design->selected(mod_it.second))
continue;
OptReduceWorker worker(design, mod_it.second, do_fine);
extra_args(args, 1, design);
- for (auto &mod_it : design->modules)
+ for (auto &mod_it : design->modules_)
{
if (!design->selected(mod_it.second))
continue;
extra_args(args, argidx, design);
int total_count = 0;
- for (auto &mod_it : design->modules) {
+ for (auto &mod_it : design->modules_) {
if (!design->selected(mod_it.second))
continue;
OptShareWorker worker(design, mod_it.second, mode_nomux);
extra_args(args, argidx, design);
- for (auto &mod_it : design->modules)
+ for (auto &mod_it : design->modules_)
if (design->selected(mod_it.second)) {
SigMap assign_map(mod_it.second);
for (auto &proc_it : mod_it.second->processes) {
extra_args(args, 1, design);
- for (auto &mod_it : design->modules) {
+ for (auto &mod_it : design->modules_) {
std::vector<std::string> delme;
if (!design->selected(mod_it.second))
continue;
extra_args(args, 1, design);
- for (auto &mod_it : design->modules)
+ for (auto &mod_it : design->modules_)
if (design->selected(mod_it.second)) {
ConstEval ce(mod_it.second);
for (auto &proc_it : mod_it.second->processes)
extra_args(args, 1, design);
- for (auto &mod_it : design->modules)
+ for (auto &mod_it : design->modules_)
if (design->selected(mod_it.second))
for (auto &proc_it : mod_it.second->processes)
if (design->selected(mod_it.second, proc_it.second))
extra_args(args, 1, design);
- for (auto &mod_it : design->modules)
+ for (auto &mod_it : design->modules_)
if (design->selected(mod_it.second))
for (auto &proc_it : mod_it.second->processes)
if (design->selected(mod_it.second, proc_it.second))
extra_args(args, 1, design);
int total_counter = 0;
- for (auto &mod_it : design->modules) {
+ for (auto &mod_it : design->modules_) {
if (!design->selected(mod_it.second))
continue;
for (auto &proc_it : mod_it.second->processes) {
{
for (auto name : split(module_list, ",")) {
RTLIL::IdString esc_name = RTLIL::escape_id(module_prefix + name);
- if (design->modules.count(esc_name) == 0)
+ if (design->modules_.count(esc_name) == 0)
log_error("Can't find module %s in current design!\n", name.c_str());
log("Using module %s (%s).\n", esc_name.c_str(), name.c_str());
- modules.push_back(design->modules.at(esc_name));
+ modules.push_back(design->modules_.at(esc_name));
module_names.push_back(name);
}
/* this should only be used for regression testing of ConstEval -- see vloghammer */
std::string mod1_name = RTLIL::escape_id(args[++argidx]);
std::string mod2_name = RTLIL::escape_id(args[++argidx]);
- if (design->modules.count(mod1_name) == 0)
+ if (design->modules_.count(mod1_name) == 0)
log_error("Can't find module `%s'!\n", mod1_name.c_str());
- if (design->modules.count(mod2_name) == 0)
+ if (design->modules_.count(mod2_name) == 0)
log_error("Can't find module `%s'!\n", mod2_name.c_str());
- BruteForceEquivChecker checker(design->modules.at(mod1_name), design->modules.at(mod2_name), args[argidx-2] == "-brute_force_equiv_checker_x");
+ BruteForceEquivChecker checker(design->modules_.at(mod1_name), design->modules_.at(mod2_name), args[argidx-2] == "-brute_force_equiv_checker_x");
if (checker.errors > 0)
log_cmd_error("Modules are not equivialent!\n");
log("Verified %s = %s (using brute-force check on %d cases).\n",
extra_args(args, argidx, design);
RTLIL::Module *module = NULL;
- for (auto &mod_it : design->modules)
+ for (auto &mod_it : design->modules_)
if (design->selected(mod_it.second)) {
if (module)
log_cmd_error("Only one module must be selected for the EVAL pass! (selected: %s and %s)\n",
{
if (cell->name[0] == '$' || dff_cells.count(cell->name))
return false;
- if (cell->type.at(0) == '\\' && !design->modules.count(cell->type))
+ if (cell->type.at(0) == '\\' && !design->modules_.count(cell->type))
return false;
return true;
}
RTLIL::Module *first_module = NULL;
std::set<std::string> shared_dff_wires;
- for (auto &mod_it : design->modules)
+ for (auto &mod_it : design->modules_)
{
if (!design->selected(mod_it.second))
continue;
{
RTLIL::Module *first_module = NULL;
- for (auto &mod_it : design->modules)
+ for (auto &mod_it : design->modules_)
{
RTLIL::Module *module = mod_it.second;
}
}
- for (auto &mod_it : design->modules)
+ for (auto &mod_it : design->modules_)
{
RTLIL::Module *module = mod_it.second;
RTLIL::Cell *cell = it.second;
- if (design->modules.count(cell->type))
+ if (design->modules_.count(cell->type))
{
- RTLIL::Module *mod = design->modules.at(cell->type);
+ RTLIL::Module *mod = design->modules_.at(cell->type);
for (auto &it : mod->wires_)
{
extra_args(args, argidx, design);
int bitcount = 0;
- for (auto &mod_it : design->modules) {
+ for (auto &mod_it : design->modules_) {
RTLIL::Module *module = mod_it.second;
if (design->selected(module))
bitcount += FreduceWorker(design, module).run();
std::string gate_name = RTLIL::escape_id(args[argidx++]);
std::string miter_name = RTLIL::escape_id(args[argidx++]);
- if (design->modules.count(gold_name) == 0)
+ if (design->modules_.count(gold_name) == 0)
log_cmd_error("Can't find gold module %s!\n", gold_name.c_str());
- if (design->modules.count(gate_name) == 0)
+ if (design->modules_.count(gate_name) == 0)
log_cmd_error("Can't find gate module %s!\n", gate_name.c_str());
- if (design->modules.count(miter_name) != 0)
+ if (design->modules_.count(miter_name) != 0)
log_cmd_error("There is already a module %s!\n", gate_name.c_str());
- RTLIL::Module *gold_module = design->modules.at(gold_name);
- RTLIL::Module *gate_module = design->modules.at(gate_name);
+ RTLIL::Module *gold_module = design->modules_.at(gold_name);
+ RTLIL::Module *gate_module = design->modules_.at(gate_name);
for (auto &it : gold_module->wires_) {
RTLIL::Wire *w1 = it.second, *w2;
RTLIL::Module *miter_module = new RTLIL::Module;
miter_module->name = miter_name;
- design->modules[miter_name] = miter_module;
+ design->modules_[miter_name] = miter_module;
RTLIL::Cell *gold_cell = miter_module->addCell("\\gold", gold_name);
RTLIL::Cell *gate_cell = miter_module->addCell("\\gate", gate_name);
extra_args(args, argidx, design);
RTLIL::Module *module = NULL;
- for (auto &mod_it : design->modules)
+ for (auto &mod_it : design->modules_)
if (design->selected(mod_it.second)) {
if (module)
log_cmd_error("Only one module must be selected for the SAT pass! (selected: %s and %s)\n",
}
extra_args(args, argidx, design);
- for (auto &mod_it : design->modules)
+ for (auto &mod_it : design->modules_)
if (design->selected(mod_it.second))
ShareWorker(config, design, mod_it.second);
}
log(" final dff cell mappings:\n");
logmap_all();
- for (auto &it : design->modules)
+ for (auto &it : design->modules_)
if (design->selected(it.second) && !it.second->get_bool_attribute("\\blackbox"))
dfflibmap(design, it.second);
delete map;
log_cmd_error("Can't saved design `%s'.\n", filename.c_str()+1);
}
- for (auto &it : saved_designs.at(filename.substr(1))->modules)
- if (!map->modules.count(it.first))
- map->modules[it.first] = it.second->clone();
+ for (auto &it : saved_designs.at(filename.substr(1))->modules_)
+ if (!map->modules_.count(it.first))
+ map->modules_[it.first] = it.second->clone();
}
else
{
log_header("Creating graphs for SubCircuit library.\n");
if (!mine_mode)
- for (auto &mod_it : map->modules) {
+ for (auto &mod_it : map->modules_) {
SubCircuit::Graph mod_graph;
std::string graph_name = "needle_" + RTLIL::unescape_id(mod_it.first);
log("Creating needle graph %s.\n", graph_name.c_str());
}
}
- for (auto &mod_it : design->modules) {
+ for (auto &mod_it : design->modules_) {
SubCircuit::Graph mod_graph;
std::string graph_name = "haystack_" + RTLIL::unescape_id(mod_it.first);
log("Creating haystack graph %s.\n", graph_name.c_str());
RTLIL::Module *newMod = new RTLIL::Module;
newMod->name = stringf("\\needle%05d_%s_%dx", needleCounter++, id2cstr(haystack_map.at(result.graphId)->name), result.totalMatchesAfterLimits);
- map->modules[newMod->name] = newMod;
+ map->modules_[newMod->name] = newMod;
int portCounter = 1;
for (auto wire : wires) {
}
extra_args(args, argidx, design);
- for (auto &it : design->modules)
+ for (auto &it : design->modules_)
{
module = it.second;
}
extra_args(args, argidx, design);
- for (auto &it : design->modules)
+ for (auto &it : design->modules_)
{
RTLIL::Module *module = it.second;
std::map<std::string, void(*)(RTLIL::Module*, RTLIL::Cell*)> mappers;
simplemap_get_mappers(mappers);
- for (auto &mod_it : design->modules) {
+ for (auto &mod_it : design->modules_) {
if (!design->selected(mod_it.second))
continue;
std::vector<RTLIL::Cell*> delete_cells;
for (auto &tpl_name : celltypeMap.at(cell->type))
{
std::string derived_name = tpl_name;
- RTLIL::Module *tpl = map->modules[tpl_name];
+ RTLIL::Module *tpl = map->modules_[tpl_name];
std::map<RTLIL::IdString, RTLIL::Const> parameters = cell->parameters;
if (tpl->get_bool_attribute("\\blackbox"))
} else {
if (cell->parameters.size() != 0) {
derived_name = tpl->derive(map, parameters);
- tpl = map->modules[derived_name];
+ tpl = map->modules_[derived_name];
log_continue = true;
}
techmap_cache[key] = tpl;
}
std::map<RTLIL::IdString, RTLIL::Module*> modules_new;
- for (auto &it : map->modules) {
+ for (auto &it : map->modules_) {
if (it.first.substr(0, 2) == "\\$")
it.second->name = it.first.substr(1);
modules_new[it.second->name] = it.second;
}
- map->modules.swap(modules_new);
+ map->modules_.swap(modules_new);
std::map<RTLIL::IdString, std::set<RTLIL::IdString>> celltypeMap;
- for (auto &it : map->modules) {
+ for (auto &it : map->modules_) {
if (it.second->attributes.count("\\techmap_celltype") && !it.second->attributes.at("\\techmap_celltype").bits.empty()) {
char *p = strdup(it.second->attributes.at("\\techmap_celltype").decode_string().c_str());
for (char *q = strtok(p, " \t\r\n"); q; q = strtok(NULL, " \t\r\n"))
std::set<RTLIL::Cell*> handled_cells;
while (did_something) {
did_something = false;
- for (auto &mod_it : design->modules)
+ for (auto &mod_it : design->modules_)
if (worker.techmap_module(design, mod_it.second, map, handled_cells, celltypeMap, false))
did_something = true;
if (did_something)
TechmapWorker worker;
std::map<RTLIL::IdString, std::set<RTLIL::IdString>> celltypeMap;
- for (auto &it : design->modules)
+ for (auto &it : design->modules_)
celltypeMap[it.first].insert(it.first);
RTLIL::Module *top_mod = NULL;
if (design->full_selection())
- for (auto &mod_it : design->modules)
+ for (auto &mod_it : design->modules_)
if (mod_it.second->get_bool_attribute("\\top"))
top_mod = mod_it.second;
if (worker.techmap_module(design, top_mod, design, handled_cells, celltypeMap, true))
did_something = true;
} else {
- for (auto &mod_it : design->modules)
+ for (auto &mod_it : design->modules_)
if (worker.techmap_module(design, mod_it.second, design, handled_cells, celltypeMap, true))
did_something = true;
}
if (top_mod != NULL) {
std::map<RTLIL::IdString, RTLIL::Module*> new_modules;
- for (auto &mod_it : design->modules)
+ for (auto &mod_it : design->modules_)
if (mod_it.second == top_mod || mod_it.second->get_bool_attribute("\\blackbox")) {
new_modules[mod_it.first] = mod_it.second;
} else {
log("Deleting now unused module %s.\n", RTLIL::id2cstr(mod_it.first));
delete mod_it.second;
}
- design->modules.swap(new_modules);
+ design->modules_.swap(new_modules);
}
log_pop();
projects / yosys.git / commitdiff