add .payload. to Sink and Source to be compatible with upstream Migen

diff --git a/lib/sata/k7sataphy/datapath.py b/lib/sata/k7sataphy/datapath.py
index 2a607b37d7b5c1ed07c0d467d52a64a1af33d760..11641be3d1329102fde4bd9184cc99d3388cbac0 100644 (file)
--- a/lib/sata/k7sataphy/datapath.py
+++ b/lib/sata/k7sataphy/datapath.py
@@ -20,8 +20,8 @@ class K7SATAPHYDatapathRX(Module):
                data_sr_d = Signal(32+8)
                charisk_sr_d = Signal(4+1)
                self.comb += [
-                       data_sr.eq(Cat(self.sink.data, data_sr_d)),
-                       charisk_sr.eq(Cat(self.sink.charisk, charisk_sr_d))
+                       data_sr.eq(Cat(self.sink.payload.data, data_sr_d)),
+                       charisk_sr.eq(Cat(self.sink.payload.charisk, charisk_sr_d))
                ]
                self.sync.sata_rx += [
                        data_sr_d.eq(data_sr),
@@ -32,8 +32,8 @@ class K7SATAPHYDatapathRX(Module):
                alignment = Signal()
                valid = Signal()
                self.sync.sata_rx += [
-                       If(self.sink.charisk !=0,
-                               alignment.eq(self.sink.charisk[1]),
+                       If(self.sink.payload.charisk !=0,
+                               alignment.eq(self.sink.payload.charisk[1]),
                                valid.eq(0)
                        ).Else(
                                valid.eq(~valid)
@@ -64,8 +64,8 @@ class K7SATAPHYDatapathRX(Module):
                self.submodules.fifo = RenameClockDomains(fifo, {"write": "sata_rx", "read": "sys"})
                self.comb += [
                        fifo.sink.stb.eq(valid),
-                       fifo.sink.data.eq(data),
-                       fifo.sink.charisk.eq(charisk),
+                       fifo.sink.payload.data.eq(data),
+                       fifo.sink.payload.charisk.eq(charisk),
                ]
                self.comb += Record.connect(fifo.source, self.source)
 
@@ -104,8 +104,8 @@ class K7SATAPHYDatapathTX(Module):
                        )
                ]
                self.comb += [
-                       chooser(fifo.source.data, mux, self.source.data),
-                       chooser(fifo.source.charisk, mux, self.source.charisk)
+                       chooser(fifo.source.payload.data, mux, self.source.payload.data),
+                       chooser(fifo.source.payload.charisk, mux, self.source.payload.charisk)
                ]
 
 class K7SATAPHYDatapath(Module):
@@ -120,11 +120,11 @@ class K7SATAPHYDatapath(Module):
                tx = K7SATAPHYDatapathTX()
                self.submodules += rx, tx
                self.comb += [
-                       rx.sink.data.eq(gtx.rxdata),
-                       rx.sink.charisk.eq(gtx.rxcharisk),
+                       rx.sink.payload.data.eq(gtx.rxdata),
+                       rx.sink.payload.charisk.eq(gtx.rxcharisk),
 
-                       gtx.txdata.eq(tx.source.data),
-                       gtx.txcharisk.eq(tx.source.charisk),
+                       gtx.txdata.eq(tx.source.payload.data),
+                       gtx.txcharisk.eq(tx.source.payload.charisk),
                ]
 
        # user / ctrl mux
@@ -132,20 +132,20 @@ class K7SATAPHYDatapath(Module):
                        # user
                        If(ctrl.ready,
                                tx.sink.stb.eq(self.sink.stb),
-                               tx.sink.data.eq(self.sink.d),
-                               tx.sink.charisk.eq(0),
+                               tx.sink.payload.data.eq(self.sink.payload.d),
+                               tx.sink.payload.charisk.eq(0),
                                self.sink.ack.eq(tx.sink.ack),
 
                                self.source.stb.eq(rx.source.stb),
-                               self.source.d.eq(rx.source.data),
+                               self.source.payload.d.eq(rx.source.payload.data),
                                rx.source.ack.eq(1),
                        # ctrl
                        ).Else(
                                tx.sink.stb.eq(1),
-                               tx.sink.data.eq(ctrl.txdata),
-                               tx.sink.charisk.eq(ctrl.txcharisk),
+                               tx.sink.payload.data.eq(ctrl.txdata),
+                               tx.sink.payload.charisk.eq(ctrl.txcharisk),
 
-                               ctrl.rxdata.eq(rx.source.data),
+                               ctrl.rxdata.eq(rx.source.payload.data),
                                rx.source.ack.eq(1),
                        )                       
                ]

diff --git a/targets/test.py b/targets/test.py
index 1e4fa8dc491e35652b31edb90c7f35923d2cade2..df2535b64ff80a6bf8bff6602bb49f696d501c89 100644 (file)
--- a/targets/test.py
+++ b/targets/test.py
@@ -102,7 +102,7 @@ class TestDesign(UART2WB):
                        host=True, default_speed="SATA3")
                self.comb += [
                        self.sataphy_host.sink.stb.eq(1),
-                       self.sataphy_host.sink.d.eq(0x12345678)
+                       self.sataphy_host.sink.payload.d.eq(0x12345678)
                ]
 
                import os