class MiIo(Module, AutoCSR):
def __init__(self, width):
- self.width = width
-
- self.i = Signal(width)
- self.o = Signal(width)
-
self._r_i = CSRStatus(width)
self._r_o = CSRStorage(width)
- self.sync += [
- self._r_i.status.eq(self.i),
- self.o.eq(self._r_o.storage)
- ]
+ self.i = self._r_i.status
+ self.o = self._r_o.storage
from migen.fhdl.structure import *
from migen.bank.description import *
-from migen.genlib.record import *
from miscope.std import *
from miscope.trigger import Trigger
self.sink = Record(dat_layout(width))
- trigger = Trigger(width, ports)
- recorder = Recorder(width, depth)
-
- self.submodules.trigger = trigger
- self.submodules.recorder = recorder
-
- sink_d = Record(dat_layout(width))
- self.sync += sink_d.eq(self.sink)
+ self.submodules.trigger = trigger = Trigger(width, ports)
+ self.submodules.recorder = recorder = Recorder(width, depth)
self.comb += [
- sink_d.connect(trigger.sink),
+ self.sink.connect(trigger.sink),
trigger.source.connect(recorder.trig_sink)
]
recorder_dat_source = self.sink
if with_rle:
- self.submodules.rle = RunLengthEncoder(width)
- self.comb += sink_d.connect(self.rle.sink)
- recorder_dat_source = self.rle.source
- self.comb += recorder_dat_source.connect(recorder.dat_sink)
+ self.submodules.rle = rle = RunLengthEncoder(width)
+ self.comb += [
+ self.sink.connect(rle.sink),
+ rle.source.connect(recorder.dat_sink)
+ ]
+ else:
+ self.sink.connect(recorder.dat_sink)
def get_csv(self, layout, ns):
r = ""
self.sink = Record(dat_layout(width))
self.source = Record(dat_layout(width))
- self._r_enable = CSRStorage()
-
+ self._enable = CSRStorage()
+
###
- enable = self._r_enable.storage
+ enable = self._enable.storage
sink_d = Record(dat_layout(width))
self.sync += If(self.sink.stb, sink_d.eq(self.sink))
self.trig_sink = Record(hit_layout())
self.dat_sink = Record(dat_layout(width))
- self._r_trigger = CSR()
- self._r_length = CSRStorage(bits_for(depth))
- self._r_offset = CSRStorage(bits_for(depth))
- self._r_done = CSRStatus()
+ self._trigger = CSR()
+ self._length = CSRStorage(bits_for(depth))
+ self._offset = CSRStorage(bits_for(depth))
+ self._done = CSRStatus()
- self._r_read_en = CSR()
- self._r_read_empty = CSRStatus()
- self._r_read_dat = CSRStatus(width)
+ self._read_en = CSR()
+ self._read_empty = CSRStatus()
+ self._read_dat = CSRStatus(width)
###
self.comb += [
- self._r_read_empty.status.eq(~fifo.readable),
- self._r_read_dat.status.eq(fifo.dout),
+ self._read_empty.status.eq(~fifo.readable),
+ self._read_dat.status.eq(fifo.dout),
]
fsm.act("IDLE",
- If(self._r_trigger.re & self._r_trigger.r,
+ If(self._trigger.re & self._trigger.r,
NextState("PRE_HIT_RECORDING"),
fifo.reset.eq(1),
),
- fifo.re.eq(self._r_read_en.re & self._r_read_en.r),
- self._r_done.status.eq(1)
+ fifo.re.eq(self._read_en.re & self._read_en.r),
+ self._done.status.eq(1)
)
-
+
fsm.act("PRE_HIT_RECORDING",
fifo.we.eq(self.dat_sink.stb),
fifo.din.eq(self.dat_sink.dat),
- fifo.re.eq(fifo.level >= self._r_offset.storage),
+ fifo.re.eq(fifo.level >= self._offset.storage),
If(self.trig_sink.stb & self.trig_sink.hit, NextState("POST_HIT_RECORDING"))
)
fifo.we.eq(self.dat_sink.stb),
fifo.din.eq(self.dat_sink.dat),
- If(~fifo.writable | (fifo.level >= self._r_length.storage), NextState("IDLE"))
+ If(~fifo.writable | (fifo.level >= self._length.storage), NextState("IDLE"))
)
self.sink = Record(dat_layout(width))
self.source = Record(hit_layout())
- self._r_trig = CSRStorage(width)
- self._r_mask = CSRStorage(width)
+ self._trig = CSRStorage(width)
+ self._mask = CSRStorage(width)
###
- trig = self._r_trig.storage
- mask = self._r_mask.storage
+ trig = self._trig.storage
+ mask = self._mask.storage
dat = self.sink.dat
hit = self.source.hit
self.sink = Record(dat_layout(width))
self.source = Record(hit_layout())
- self._r_low = CSRStorage(width)
- self._r_high = CSRStorage(width)
+ self._low = CSRStorage(width)
+ self._high = CSRStorage(width)
###
- low = self._r_low.storage
- high = self._r_high.storage
+ low = self._low.storage
+ high = self._high.storage
dat = self.sink.dat
hit = self.source.hit
class EdgeDetector(Module, AutoCSR):
def __init__(self, width):
self.width = width
-
+
self.sink = Record(dat_layout(width))
self.source = Record(hit_layout())
- self._r_rising_mask = CSRStorage(width)
- self._r_falling_mask = CSRStorage(width)
- self._r_both_mask = CSRStorage(width)
+ self._rising_mask = CSRStorage(width)
+ self._falling_mask = CSRStorage(width)
+ self._both_mask = CSRStorage(width)
###
- rising_mask = self._r_rising_mask.storage
- falling_mask = self._r_falling_mask.storage
- both_mask = self._r_both_mask.storage
+ rising_mask = self._rising_mask.storage
+ falling_mask = self._falling_mask.storage
+ both_mask = self._both_mask.storage
dat = self.sink.dat
dat_d = Signal(width)
self.sinks = [Record(hit_layout()) for p in range(ports)]
self.source = Record(hit_layout())
-
- self._r_prog_we = CSRStorage()
- self._r_prog_adr = CSRStorage(ports) #FIXME
- self._r_prog_dat = CSRStorage()
+
+ self._prog_we = CSRStorage()
+ self._prog_adr = CSRStorage(ports) #FIXME
+ self._prog_dat = CSRStorage()
mem = Memory(1, 2**ports)
lut_port = mem.get_port()
# Lut prog
self.comb += [
- prog_port.we.eq(self._r_prog_we.storage),
- prog_port.adr.eq(self._r_prog_adr.storage),
- prog_port.dat_w.eq(self._r_prog_dat.storage)
+ prog_port.we.eq(self._prog_we.storage),
+ prog_port.adr.eq(self._prog_adr.storage),
+ prog_port.dat_w.eq(self._prog_dat.storage)
]
# Lut read
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