log_abort();
continue;
}
- cell = module->addCell(remap_name(c->name), c->type);
+ cell = module->addCell(remap_name(mapped_cell->name), mapped_cell->type);
}
else {
- existing_cell = module->cell(c->name);
+ existing_cell = module->cell(mapped_cell->name);
log_assert(existing_cell);
- cell = module->addCell(remap_name(c->name), c->type);
+ cell = module->addCell(remap_name(mapped_cell->name), mapped_cell->type);
- module->swap_names(cell, existing_cell);
}
if (markgroups) cell->attributes[ID(abcgroup)] = map_autoidx;
// ============================================================================
+module FDRE (output reg Q, input C, CE, D, R);
+ parameter [0:0] INIT = 1'b0;
+ parameter [0:0] IS_C_INVERTED = 1'b0;
+ parameter [0:0] IS_D_INVERTED = 1'b0;
+ parameter [0:0] IS_R_INVERTED = 1'b0;
+ wire \$nextQ ;
+ FDRE #(
+ .INIT(INIT),
+ .IS_C_INVERTED(IS_C_INVERTED),
+ .IS_D_INVERTED(IS_D_INVERTED),
+ .IS_R_INVERTED(IS_R_INVERTED)
+ ) _TECHMAP_REPLACE_ (
+ .D(D), .Q(\$nextQ ), .\$currQ (Q), .C(C), .CE(CE), .R(R)
+ );
+ \$__ABC_FF_ abc_dff (.D(\$nextQ ), .Q(Q));
+endmodule
+module FDRE_1 (output reg Q, input C, CE, D, R);
+ parameter [0:0] INIT = 1'b0;
+ wire \$nextQ ;
+ FDRE_1 #(
+ .INIT(|0),
+ ) _TECHMAP_REPLACE_ (
+ .D(D), .Q(\$nextQ ), .\$currQ (Q), .C(C), .CE(CE), .R(R)
+ );
+ \$__ABC_FF_ abc_dff (.D(\$nextQ ), .Q(Q));
+endmodule
+
+module FDCE (output reg Q, input C, CE, D, CLR);
+ parameter [0:0] INIT = 1'b0;
+ parameter [0:0] IS_C_INVERTED = 1'b0;
+ parameter [0:0] IS_D_INVERTED = 1'b0;
+ parameter [0:0] IS_CLR_INVERTED = 1'b0;
+ wire \$nextQ , \$currQ ;
+ FDCE #(
+ .INIT(INIT),
+ .IS_C_INVERTED(IS_C_INVERTED),
+ .IS_D_INVERTED(IS_D_INVERTED),
+ .IS_CLR_INVERTED(IS_CLR_INVERTED)
+ ) _TECHMAP_REPLACE_ (
+ .D(D), .Q(\$nextQ ), .\$currQ (Q), .C(C), .CE(CE), .CLR(CLR)
+ );
+ \$__ABC_FF_ abc_dff (.D(\$nextQ ), .Q(\$currQ ));
+ \$__ABC_ASYNC abc_async (.A(\$currQ ), .S(CLR ^ IS_CLR_INVERTED), .Y(Q));
+endmodule
+module FDCE_1 (output reg Q, input C, CE, D, CLR);
+ parameter [0:0] INIT = 1'b0;
+ wire \$nextQ , \$currQ ;
+ FDCE_1 #(
+ .INIT(INIT)
+ ) _TECHMAP_REPLACE_ (
+ .D(D), .Q(\$nextQ ), .\$currQ (Q), .C(C), .CE(CE), .CLR(CLR)
+ );
+ \$__ABC_FF_ abc_dff (.D(\$nextQ ), .Q(\$currQ ));
+ \$__ABC_ASYNC abc_async (.A(\$currQ ), .S(CLR), .Y(Q));
+endmodule
+
+module FDPE (output reg Q, input C, CE, D, PRE);
+ parameter [0:0] INIT = 1'b0;
+ parameter [0:0] IS_C_INVERTED = 1'b0;
+ parameter [0:0] IS_D_INVERTED = 1'b0;
+ parameter [0:0] IS_PRE_INVERTED = 1'b0;
+ wire \$nextQ , \$currQ ;
+ FDPE #(
+ .INIT(INIT),
+ .IS_C_INVERTED(IS_C_INVERTED),
+ .IS_D_INVERTED(IS_D_INVERTED),
+ .IS_PRE_INVERTED(IS_PRE_INVERTED),
+ ) _TECHMAP_REPLACE_ (
+ .D(D), .Q(\$nextQ ), .\$currQ (Q), .C(C), .CE(CE), .PRE(PRE)
+ );
+ \$__ABC_FF_ abc_dff (.D(\$nextQ ), .Q(\$currQ ));
+ \$__ABC_ASYNC abc_async (.A(\$currQ ), .S(PRE ^ IS_PRE_INVERTED), .Y(Q));
+endmodule
+module FDPE_1 (output reg Q, input C, CE, D, PRE);
+ parameter [0:0] INIT = 1'b0;
+ wire \$nextQ , \$currQ ;
+ FDPE_1 #(
+ .INIT(INIT)
+ ) _TECHMAP_REPLACE_ (
+ .D(D), .Q(\$nextQ ), .\$currQ (Q), .C(C), .CE(CE), .PRE(PRE)
+ );
+ \$__ABC_FF_ abc_dff (.D(\$nextQ ), .Q(\$currQ ));
+ \$__ABC_ASYNC abc_async (.A(\$currQ ), .S(PRE), .Y(Q));
+endmodule
+
+module FDSE (output reg Q, input C, CE, D, S);
+ parameter [0:0] INIT = 1'b0;
+ parameter [0:0] IS_C_INVERTED = 1'b0;
+ parameter [0:0] IS_D_INVERTED = 1'b0;
+ parameter [0:0] IS_S_INVERTED = 1'b0;
+ wire \$nextQ ;
+ FDSE #(
+ .INIT(INIT),
+ .IS_C_INVERTED(IS_C_INVERTED),
+ .IS_D_INVERTED(IS_D_INVERTED),
+ .IS_S_INVERTED(IS_S_INVERTED)
+ ) _TECHMAP_REPLACE_ (
+ .D(D), .Q(\$nextQ ), .\$currQ (Q), .C(C), .CE(CE), .S(S)
+ );
+ \$__ABC_FF_ abc_dff (.D(\$nextQ ), .Q(Q));
+endmodule
+module FDSE_1 (output reg Q, input C, CE, D, S);
+ parameter [0:0] INIT = 1'b0;
+ wire \$nextQ ;
+ FDSE_1 #(
+ .INIT(|0),
+ ) _TECHMAP_REPLACE_ (
+ .D(D), .Q(\$nextQ ), .\$currQ (Q), .C(C), .CE(CE), .S(S)
+ );
+ \$__ABC_FF_ abc_dff (.D(\$nextQ ), .Q(Q));
+endmodule
+
module RAM32X1D (
output DPO, SPO,
- input D,
- input WCLK,
- input WE,
- input A0, A1, A2, A3, A4,
- input DPRA0, DPRA1, DPRA2, DPRA3, DPRA4
+ (* techmap_autopurge *) input D,
+ (* techmap_autopurge *) input WCLK,
+ (* techmap_autopurge *) input WE,
+ (* techmap_autopurge *) input A0, A1, A2, A3, A4,
+ (* techmap_autopurge *) input DPRA0, DPRA1, DPRA2, DPRA3, DPRA4
);
parameter INIT = 32'h0;
parameter IS_WCLK_INVERTED = 1'b0;
: (S0 ? I1 : I0);
endmodule
+module \$__ABC_FF_ (input D, output Q);
+endmodule
+
+(* abc_box_id = 1000 *)
+module \$__ABC_ASYNC (input A, S, output Y);
++
+ // Box to emulate comb/seq behaviour of RAMD{32,64} and SRL{16,32}
+ // Necessary since RAMD* and SRL* have both combinatorial (i.e.
+ // same-cycle read operation) and sequential (write operation
+ // is only committed on the next clock edge).
+ // To model the combinatorial path, such cells have to be split
+ // into comb and seq parts, with this box modelling only the former.
+ (* abc_box_id=2000 *)
+ module \$__ABC_LUT6 (input A, input [5:0] S, output Y);
+ endmodule
+ // Box to emulate comb/seq behaviour of RAMD128
+ (* abc_box_id=2001 *)
+ module \$__ABC_LUT7 (input A, input [6:0] S, output Y);
+ endmodule
+
+
+ // Modules used to model the comb/seq behaviour of DSP48E1
+ // With abc_map.v responsible for splicing the below modules
+ // between the combinatorial DSP48E1 box (e.g. disconnecting
+ // A when AREG, MREG or PREG is enabled and splicing in the
+ // "$__ABC_DSP48E1_REG" blackbox as "REG" in the diagram below)
+ // this acts to first disables the combinatorial path (as there
+ // is no connectivity through REG), and secondly, since this is
+ // blackbox a new PI will be introduced with an arrival time of
+ // zero.
+ // Note: Since these "$__ABC_DSP48E1_REG" modules are of a
+ // sequential nature, they are not passed as a box to ABC and
+ // (desirably) represented as PO/PIs.
+ //
+ // At the DSP output, we place a blackbox mux ("M" in the diagram
+ // below) to capture the fact that the critical-path could come
+ // from any one of its inputs.
+ // In contrast to "REG", the "$__ABC_DSP48E1_*_MUX" modules are
+ // combinatorial blackboxes that do get passed to ABC.
+ // The propagation delay through this box (specified in the box
+ // file) captures the arrival time of the register (i.e.
+ // propagation from AREG to P after clock edge), or zero delay
+ // for the combinatorial path from the DSP.
+ //
+ // Doing so should means that ABC is able to analyse the
+ // worst-case delay through to P, regardless of if it was
+ // through any combinatorial paths (e.g. B, below) or an
+ // internal register (A2REG).
+ // However, the true value of being as complete as this is
+ // questionable since if AREG=1 and BREG=0 (as below)
+ // then the worse-case path would very likely be through B
+ // and very unlikely to be through AREG.Q...?
+ //
+ // In graphical form:
+ //
+ // +-----+
+ // +------>> REG >>----+
+ // | +-----+ |
+ // | |
+ // | +---------+ | __
+ // A >>-+X X-| | +--| \
+ // | DSP48E1 |P | M |--->> P
+ // | AREG=1 |-------|__/
+ // B >>------| |
+ // +---------+
+ //
+ `define ABC_DSP48E1_MUX(__NAME__) """
+ module __NAME__ (input Aq, ADq, Bq, Cq, Dq, input [47:0] I, input Mq, input [47:0] P, input Pq, output [47:0] O);
+ endmodule
+ """
+ (* abc_box_id=2100 *) `ABC_DSP48E1_MUX(\$__ABC_DSP48E1_MULT_P_MUX )
+ (* abc_box_id=2101 *) `ABC_DSP48E1_MUX(\$__ABC_DSP48E1_MULT_PCOUT_MUX )
+ (* abc_box_id=2102 *) `ABC_DSP48E1_MUX(\$__ABC_DSP48E1_MULT_DPORT_P_MUX )
+ (* abc_box_id=2103 *) `ABC_DSP48E1_MUX(\$__ABC_DSP48E1_MULT_DPORT_PCOUT_MUX )
+ (* abc_box_id=2104 *) `ABC_DSP48E1_MUX(\$__ABC_DSP48E1_P_MUX )
+ (* abc_box_id=2105 *) `ABC_DSP48E1_MUX(\$__ABC_DSP48E1_PCOUT_MUX )
+
+ `define ABC_DSP48E1(__NAME__) """
+ module __NAME__ (
+ output [29:0] ACOUT,
+ output [17:0] BCOUT,
+ output reg CARRYCASCOUT,
+ output reg [3:0] CARRYOUT,
+ output reg MULTSIGNOUT,
+ output OVERFLOW,
+ output reg signed [47:0] P,
+ output PATTERNBDETECT,
+ output PATTERNDETECT,
+ output [47:0] PCOUT,
+ output UNDERFLOW,
+ input signed [29:0] A,
+ input [29:0] ACIN,
+ input [3:0] ALUMODE,
+ input signed [17:0] B,
+ input [17:0] BCIN,
+ input [47:0] C,
+ input CARRYCASCIN,
+ input CARRYIN,
+ input [2:0] CARRYINSEL,
+ input CEA1,
+ input CEA2,
+ input CEAD,
+ input CEALUMODE,
+ input CEB1,
+ input CEB2,
+ input CEC,
+ input CECARRYIN,
+ input CECTRL,
+ input CED,
+ input CEINMODE,
+ input CEM,
+ input CEP,
+ input CLK,
+ input [24:0] D,
+ input [4:0] INMODE,
+ input MULTSIGNIN,
+ input [6:0] OPMODE,
+ input [47:0] PCIN,
+ input RSTA,
+ input RSTALLCARRYIN,
+ input RSTALUMODE,
+ input RSTB,
+ input RSTC,
+ input RSTCTRL,
+ input RSTD,
+ input RSTINMODE,
+ input RSTM,
+ input RSTP
+ );
+ parameter integer ACASCREG = 1;
+ parameter integer ADREG = 1;
+ parameter integer ALUMODEREG = 1;
+ parameter integer AREG = 1;
+ parameter AUTORESET_PATDET = "NO_RESET";
+ parameter A_INPUT = "DIRECT";
+ parameter integer BCASCREG = 1;
+ parameter integer BREG = 1;
+ parameter B_INPUT = "DIRECT";
+ parameter integer CARRYINREG = 1;
+ parameter integer CARRYINSELREG = 1;
+ parameter integer CREG = 1;
+ parameter integer DREG = 1;
+ parameter integer INMODEREG = 1;
+ parameter integer MREG = 1;
+ parameter integer OPMODEREG = 1;
+ parameter integer PREG = 1;
+ parameter SEL_MASK = "MASK";
+ parameter SEL_PATTERN = "PATTERN";
+ parameter USE_DPORT = "FALSE";
+ parameter USE_MULT = "MULTIPLY";
+ parameter USE_PATTERN_DETECT = "NO_PATDET";
+ parameter USE_SIMD = "ONE48";
+ parameter [47:0] MASK = 48'h3FFFFFFFFFFF;
+ parameter [47:0] PATTERN = 48'h000000000000;
+ parameter [3:0] IS_ALUMODE_INVERTED = 4'b0;
+ parameter [0:0] IS_CARRYIN_INVERTED = 1'b0;
+ parameter [0:0] IS_CLK_INVERTED = 1'b0;
+ parameter [4:0] IS_INMODE_INVERTED = 5'b0;
+ parameter [6:0] IS_OPMODE_INVERTED = 7'b0;
endmodule
+ """
+ (* abc_box_id=3000 *) `ABC_DSP48E1(\$__ABC_DSP48E1_MULT )
+ (* abc_box_id=3001 *) `ABC_DSP48E1(\$__ABC_DSP48E1_MULT_DPORT )
+ (* abc_box_id=3002 *) `ABC_DSP48E1(\$__ABC_DSP48E1 )
// ============================================================================
-module \$__ABC_LUT6 (input A, input [5:0] S, output Y);
+module \$__ABC_ASYNC (input A, S, output Y);
assign Y = A;
endmodule
-module \$__ABC_LUT7 (input A, input [6:0] S, output Y);
- assign Y = A;
+
+module \$__ABC_FF_ (input D, output Q);
+ assign Q = D;
endmodule
+
+ module \$__ABC_REG (input [WIDTH-1:0] I, output [WIDTH-1:0] O, output Q);
+ parameter WIDTH = 1;
+ assign O = I;
+ endmodule
+ (* techmap_celltype = "$__ABC_DSP48E1_MULT_P_MUX $__ABC_DSP48E1_MULT_PCOUT_MUX $__ABC_DSP48E1_MULT_DPORT_P_MUX $__ABC_DSP48E1_MULT_DPORT_PCOUT_MUX $__ABC_DSP48E1_P_MUX $__ABC_DSP48E1_PCOUT_MUX" *)
+ module \$__ABC_DSP48E1_MUX (
+ input Aq, Bq, Cq, Dq, ADq,
+ input [47:0] I,
+ input Mq,
+ input [47:0] P,
+ input Pq,
+ output [47:0] O
+ );
+ assign O = I;
+ endmodule
+
+ (* techmap_celltype = "$__ABC_DSP48E1_MULT $__ABC_DSP48E1_MULT_DPORT $__ABC_DSP48E1" *)
+ module \$__ABC_DSP48E1 (
+ (* techmap_autopurge *) output [29:0] ACOUT,
+ (* techmap_autopurge *) output [17:0] BCOUT,
+ (* techmap_autopurge *) output reg CARRYCASCOUT,
+ (* techmap_autopurge *) output reg [3:0] CARRYOUT,
+ (* techmap_autopurge *) output reg MULTSIGNOUT,
+ (* techmap_autopurge *) output OVERFLOW,
+ (* techmap_autopurge *) output reg signed [47:0] P,
+ (* techmap_autopurge *) output PATTERNBDETECT,
+ (* techmap_autopurge *) output PATTERNDETECT,
+ (* techmap_autopurge *) output [47:0] PCOUT,
+ (* techmap_autopurge *) output UNDERFLOW,
+ (* techmap_autopurge *) input signed [29:0] A,
+ (* techmap_autopurge *) input [29:0] ACIN,
+ (* techmap_autopurge *) input [3:0] ALUMODE,
+ (* techmap_autopurge *) input signed [17:0] B,
+ (* techmap_autopurge *) input [17:0] BCIN,
+ (* techmap_autopurge *) input [47:0] C,
+ (* techmap_autopurge *) input CARRYCASCIN,
+ (* techmap_autopurge *) input CARRYIN,
+ (* techmap_autopurge *) input [2:0] CARRYINSEL,
+ (* techmap_autopurge *) input CEA1,
+ (* techmap_autopurge *) input CEA2,
+ (* techmap_autopurge *) input CEAD,
+ (* techmap_autopurge *) input CEALUMODE,
+ (* techmap_autopurge *) input CEB1,
+ (* techmap_autopurge *) input CEB2,
+ (* techmap_autopurge *) input CEC,
+ (* techmap_autopurge *) input CECARRYIN,
+ (* techmap_autopurge *) input CECTRL,
+ (* techmap_autopurge *) input CED,
+ (* techmap_autopurge *) input CEINMODE,
+ (* techmap_autopurge *) input CEM,
+ (* techmap_autopurge *) input CEP,
+ (* techmap_autopurge *) input CLK,
+ (* techmap_autopurge *) input [24:0] D,
+ (* techmap_autopurge *) input [4:0] INMODE,
+ (* techmap_autopurge *) input MULTSIGNIN,
+ (* techmap_autopurge *) input [6:0] OPMODE,
+ (* techmap_autopurge *) input [47:0] PCIN,
+ (* techmap_autopurge *) input RSTA,
+ (* techmap_autopurge *) input RSTALLCARRYIN,
+ (* techmap_autopurge *) input RSTALUMODE,
+ (* techmap_autopurge *) input RSTB,
+ (* techmap_autopurge *) input RSTC,
+ (* techmap_autopurge *) input RSTCTRL,
+ (* techmap_autopurge *) input RSTD,
+ (* techmap_autopurge *) input RSTINMODE,
+ (* techmap_autopurge *) input RSTM,
+ (* techmap_autopurge *) input RSTP
+ );
+ parameter integer ACASCREG = 1;
+ parameter integer ADREG = 1;
+ parameter integer ALUMODEREG = 1;
+ parameter integer AREG = 1;
+ parameter AUTORESET_PATDET = "NO_RESET";
+ parameter A_INPUT = "DIRECT";
+ parameter integer BCASCREG = 1;
+ parameter integer BREG = 1;
+ parameter B_INPUT = "DIRECT";
+ parameter integer CARRYINREG = 1;
+ parameter integer CARRYINSELREG = 1;
+ parameter integer CREG = 1;
+ parameter integer DREG = 1;
+ parameter integer INMODEREG = 1;
+ parameter integer MREG = 1;
+ parameter integer OPMODEREG = 1;
+ parameter integer PREG = 1;
+ parameter SEL_MASK = "MASK";
+ parameter SEL_PATTERN = "PATTERN";
+ parameter USE_DPORT = "FALSE";
+ parameter USE_MULT = "MULTIPLY";
+ parameter USE_PATTERN_DETECT = "NO_PATDET";
+ parameter USE_SIMD = "ONE48";
+ parameter [47:0] MASK = 48'h3FFFFFFFFFFF;
+ parameter [47:0] PATTERN = 48'h000000000000;
+ parameter [3:0] IS_ALUMODE_INVERTED = 4'b0;
+ parameter [0:0] IS_CARRYIN_INVERTED = 1'b0;
+ parameter [0:0] IS_CLK_INVERTED = 1'b0;
+ parameter [4:0] IS_INMODE_INVERTED = 5'b0;
+ parameter [6:0] IS_OPMODE_INVERTED = 7'b0;
+
+ DSP48E1 #(
+ .ACASCREG(ACASCREG),
+ .ADREG(ADREG),
+ .ALUMODEREG(ALUMODEREG),
+ .AREG(AREG),
+ .AUTORESET_PATDET(AUTORESET_PATDET),
+ .A_INPUT(A_INPUT),
+ .BCASCREG(BCASCREG),
+ .BREG(BREG),
+ .B_INPUT(B_INPUT),
+ .CARRYINREG(CARRYINREG),
+ .CARRYINSELREG(CARRYINSELREG),
+ .CREG(CREG),
+ .DREG(DREG),
+ .INMODEREG(INMODEREG),
+ .MREG(MREG),
+ .OPMODEREG(OPMODEREG),
+ .PREG(PREG),
+ .SEL_MASK(SEL_MASK),
+ .SEL_PATTERN(SEL_PATTERN),
+ .USE_DPORT(USE_DPORT),
+ .USE_MULT(USE_MULT),
+ .USE_PATTERN_DETECT(USE_PATTERN_DETECT),
+ .USE_SIMD(USE_SIMD),
+ .MASK(MASK),
+ .PATTERN(PATTERN),
+ .IS_ALUMODE_INVERTED(IS_ALUMODE_INVERTED),
+ .IS_CARRYIN_INVERTED(IS_CARRYIN_INVERTED),
+ .IS_CLK_INVERTED(IS_CLK_INVERTED),
+ .IS_INMODE_INVERTED(IS_INMODE_INVERTED),
+ .IS_OPMODE_INVERTED(IS_OPMODE_INVERTED)
+ ) _TECHMAP_REPLACE_ (
+ .ACOUT(ACOUT),
+ .BCOUT(BCOUT),
+ .CARRYCASCOUT(CARRYCASCOUT),
+ .CARRYOUT(CARRYOUT),
+ .MULTSIGNOUT(MULTSIGNOUT),
+ .OVERFLOW(OVERFLOW),
+ .P(P),
+ .PATTERNBDETECT(PATTERNBDETECT),
+ .PATTERNDETECT(PATTERNDETECT),
+ .PCOUT(PCOUT),
+ .UNDERFLOW(UNDERFLOW),
+ .A(A),
+ .ACIN(ACIN),
+ .ALUMODE(ALUMODE),
+ .B(B),
+ .BCIN(BCIN),
+ .C(C),
+ .CARRYCASCIN(CARRYCASCIN),
+ .CARRYIN(CARRYIN),
+ .CARRYINSEL(CARRYINSEL),
+ .CEA1(CEA1),
+ .CEA2(CEA2),
+ .CEAD(CEAD),
+ .CEALUMODE(CEALUMODE),
+ .CEB1(CEB1),
+ .CEB2(CEB2),
+ .CEC(CEC),
+ .CECARRYIN(CECARRYIN),
+ .CECTRL(CECTRL),
+ .CED(CED),
+ .CEINMODE(CEINMODE),
+ .CEM(CEM),
+ .CEP(CEP),
+ .CLK(CLK),
+ .D(D),
+ .INMODE(INMODE),
+ .MULTSIGNIN(MULTSIGNIN),
+ .OPMODE(OPMODE),
+ .PCIN(PCIN),
+ .RSTA(RSTA),
+ .RSTALLCARRYIN(RSTALLCARRYIN),
+ .RSTALUMODE(RSTALUMODE),
+ .RSTB(RSTB),
+ .RSTC(RSTC),
+ .RSTCTRL(RSTCTRL),
+ .RSTD(RSTD),
+ .RSTINMODE(RSTINMODE),
+ .RSTM(RSTM),
+ .RSTP(RSTP)
+ );
+ endmodule
projects / yosys.git / commitdiff