i965: Merge gen8_upload_constant_state into gen7_upload_constant_state.

The two paths are really similar, and the extra conditionals will be
dwarfed by the cost of the actual upload.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

diff --git a/src/mesa/drivers/dri/i965/brw_state.h b/src/mesa/drivers/dri/i965/brw_state.h
index 72478bae3d361b59e78ac48633e1dc4c10264571..b8e85202f0e512dd5dd0f4baba74120d3ffbcc36 100644 (file)
--- a/src/mesa/drivers/dri/i965/brw_state.h
+++ b/src/mesa/drivers/dri/i965/brw_state.h
@@ -269,11 +269,6 @@ gen7_upload_constant_state(struct brw_context *brw,
                            const struct brw_stage_state *stage_state,
                            bool active, unsigned opcode);
 
-/* gen8_vs_state.c */
-void
-gen8_upload_constant_state(struct brw_context *brw,
-                           const struct brw_stage_state *stage_state,
-                           bool active, unsigned opcode);
 #ifdef __cplusplus
 }
 #endif

diff --git a/src/mesa/drivers/dri/i965/gen7_vs_state.c b/src/mesa/drivers/dri/i965/gen7_vs_state.c
index ba4a36e7e2e57f432a4f47bcf046606f68b980cf..a0303104c17e199717668e8f52f7433ab7060d61 100644 (file)
--- a/src/mesa/drivers/dri/i965/gen7_vs_state.c
+++ b/src/mesa/drivers/dri/i965/gen7_vs_state.c
@@ -35,20 +35,30 @@ gen7_upload_constant_state(struct brw_context *brw,
                            const struct brw_stage_state *stage_state,
                            bool active, unsigned opcode)
 {
+   uint32_t mocs = brw->gen < 8 ? GEN7_MOCS_L3 : 0;
+
    /* Disable if the shader stage is inactive or there are no push constants. */
    active = active && stage_state->push_const_size != 0;
 
-   BEGIN_BATCH(7);
-   OUT_BATCH(opcode << 16 | (7 - 2));
+   int dwords = brw->gen >= 8 ? 11 : 7;
+   BEGIN_BATCH(dwords);
+   OUT_BATCH(opcode << 16 | (dwords - 2));
    OUT_BATCH(active ? stage_state->push_const_size : 0);
    OUT_BATCH(0);
    /* Pointer to the constant buffer.  Covered by the set of state flags
     * from gen6_prepare_wm_contants
     */
-   OUT_BATCH(active ? (stage_state->push_const_offset | GEN7_MOCS_L3) : 0);
+   OUT_BATCH(active ? (stage_state->push_const_offset | mocs) : 0);
    OUT_BATCH(0);
    OUT_BATCH(0);
    OUT_BATCH(0);
+   if (brw->gen >= 8) {
+      OUT_BATCH(0);
+      OUT_BATCH(0);
+      OUT_BATCH(0);
+      OUT_BATCH(0);
+   }
+
    ADVANCE_BATCH();
 }
 

diff --git a/src/mesa/drivers/dri/i965/gen8_gs_state.c b/src/mesa/drivers/dri/i965/gen8_gs_state.c
index 6774d86efa0bf3da9987c1300c78303e4b5239c8..ef25115db9254b6d14a7a6280550dda4c42c79dc 100644 (file)
--- a/src/mesa/drivers/dri/i965/gen8_gs_state.c
+++ b/src/mesa/drivers/dri/i965/gen8_gs_state.c
@@ -36,7 +36,7 @@ gen8_upload_gs_state(struct brw_context *brw)
    /* CACHE_NEW_GS_PROG */
    const struct brw_vec4_prog_data *prog_data = &brw->gs.prog_data->base;
 
-   gen8_upload_constant_state(brw, stage_state, active, _3DSTATE_CONSTANT_GS);
+   gen7_upload_constant_state(brw, stage_state, active, _3DSTATE_CONSTANT_GS);
 
    if (active) {
       int urb_entry_write_offset = 1;

diff --git a/src/mesa/drivers/dri/i965/gen8_ps_state.c b/src/mesa/drivers/dri/i965/gen8_ps_state.c
index 80091e83fada913e89caad99285f1e7bc7f57adf..f0362a276d0dff795ecc21a71e7ece630f6ccbb9 100644 (file)
--- a/src/mesa/drivers/dri/i965/gen8_ps_state.c
+++ b/src/mesa/drivers/dri/i965/gen8_ps_state.c
@@ -137,7 +137,7 @@ upload_ps_state(struct brw_context *brw)
    uint32_t dw3 = 0, dw6 = 0, dw7 = 0;
 
    /* CACHE_NEW_WM_PROG */
-   gen8_upload_constant_state(brw, &brw->wm.base, true, _3DSTATE_CONSTANT_PS);
+   gen7_upload_constant_state(brw, &brw->wm.base, true, _3DSTATE_CONSTANT_PS);
 
    /* Initialize the execution mask with VMask.  Otherwise, derivatives are
     * incorrect for subspans where some of the pixels are unlit.  We believe

diff --git a/src/mesa/drivers/dri/i965/gen8_vs_state.c b/src/mesa/drivers/dri/i965/gen8_vs_state.c
index 87854a35e3e4b6a31ad49e84b62bfb0be4741d56..9ac681fb4199753a0e6a83d95c8a520e7dbc177b 100644 (file)
--- a/src/mesa/drivers/dri/i965/gen8_vs_state.c
+++ b/src/mesa/drivers/dri/i965/gen8_vs_state.c
@@ -29,29 +29,6 @@
 #include "program/prog_statevars.h"
 #include "intel_batchbuffer.h"
 
-void
-gen8_upload_constant_state(struct brw_context *brw,
-                           const struct brw_stage_state *stage_state,
-                           bool active, unsigned opcode)
-{
-   /* Disable if the shader stage is inactive or there are no push constants. */
-   active = active && stage_state->push_const_size != 0;
-
-   BEGIN_BATCH(11);
-   OUT_BATCH(opcode << 16 | (11 - 2));
-   OUT_BATCH(active ? stage_state->push_const_size : 0);
-   OUT_BATCH(0);
-   OUT_BATCH(active ? stage_state->push_const_offset : 0);
-   OUT_BATCH(0);
-   OUT_BATCH(0);
-   OUT_BATCH(0);
-   OUT_BATCH(0);
-   OUT_BATCH(0);
-   OUT_BATCH(0);
-   OUT_BATCH(0);
-   ADVANCE_BATCH();
-}
-
 static void
 upload_vs_state(struct brw_context *brw)
 {
@@ -62,7 +39,7 @@ upload_vs_state(struct brw_context *brw)
    /* CACHE_NEW_VS_PROG */
    const struct brw_vec4_prog_data *prog_data = &brw->vs.prog_data->base;
 
-   gen8_upload_constant_state(brw, stage_state, true /* active */,
+   gen7_upload_constant_state(brw, stage_state, true /* active */,
                               _3DSTATE_CONSTANT_VS);
 
    /* Use ALT floating point mode for ARB vertex programs, because they