- fpga/arty_a7-35.xdc : {file_type : xdc}
- fpga/clk_gen_plle2.vhd : {file_type : vhdlSource-2008}
+ arty_a7-100:
+ files:
+ - fpga/arty_a7-35.xdc : {file_type : xdc}
+ - fpga/clk_gen_plle2.vhd : {file_type : vhdlSource-2008}
+
cmod_a7-35:
files:
- fpga/cmod_a7-35.xdc : {file_type : xdc}
vivado: {part : xc7a35ticsg324-1L}
toplevel : toplevel
+ arty_a7-100:
+ default_tool: vivado
+ filesets: [core, arty_a7-100, soc, fpga, debug_xilinx]
+ parameters : [memory_size, ram_init_file]
+ tools:
+ vivado: {part : xc7a100ticsg324-1L}
+ toplevel : toplevel
+
cmod_a7-35:
default_tool: vivado
filesets: [core, cmod_a7-35, soc, fpga, debug_xilinx]