emit_data->args[0], emit_data->args[1]);
}
+/* TGSI_OPCODE_ARL (CPU Only) */
+static void
+arl_emit_cpu(
+ const struct lp_build_tgsi_action * action,
+ struct lp_build_tgsi_context * bld_base,
+ struct lp_build_emit_data * emit_data)
+{
+ LLVMValueRef tmp;
+ tmp = lp_build_floor(&bld_base->base,
+ emit_data->args[0]);
+ emit_data->output[emit_data->chan] = LLVMBuildFPToSI(bld_base->base.gallivm->builder, tmp,
+ bld_base->uint_bld.vec_type, "");
+}
+
/* TGSI_OPCODE_CEIL (CPU Only) */
static void
ceil_emit_cpu(
lp_set_default_actions(bld_base);
bld_base->op_actions[TGSI_OPCODE_ABS].emit = abs_emit_cpu;
bld_base->op_actions[TGSI_OPCODE_ADD].emit = add_emit_cpu;
- bld_base->op_actions[TGSI_OPCODE_ARL].emit = flr_emit_cpu;
+ bld_base->op_actions[TGSI_OPCODE_ARL].emit = arl_emit_cpu;
bld_base->op_actions[TGSI_OPCODE_CEIL].emit = ceil_emit_cpu;
bld_base->op_actions[TGSI_OPCODE_CND].emit = cnd_emit_cpu;
bld_base->op_actions[TGSI_OPCODE_COS].emit = cos_emit_cpu;
bld->addr[indirect_reg->Index][swizzle],
"load addr reg");
- /* for indexing we want integers */
- rel = LLVMBuildFPToSI(builder,
- rel,
- uint_bld->vec_type, "");
-
index = lp_build_add(uint_bld, base, rel);
max_index = lp_build_const_int_vec(bld->bld_base.base.gallivm,
}
}
-
/**
* Register store.
*/
struct lp_build_context *uint_bld = &bld_base->uint_bld;
LLVMValueRef indirect_index = NULL;
struct lp_build_context *bld_store;
+ enum tgsi_opcode_type dtype = tgsi_opcode_infer_dst_type(inst->Instruction.Opcode);
- bld_store = &bld->bld_base.base;
+ switch (dtype) {
+ default:
+ case TGSI_TYPE_FLOAT:
+ case TGSI_TYPE_UNTYPED:
+ bld_store = &bld_base->base;
+ break;
+ case TGSI_TYPE_UNSIGNED:
+ bld_store = &bld_base->uint_bld;
+ break;
+ case TGSI_TYPE_SIGNED:
+ bld_store = &bld_base->int_bld;
+ break;
+ case TGSI_TYPE_DOUBLE:
+ case TGSI_TYPE_VOID:
+ assert(0);
+ bld_store = NULL;
+ break;
+ }
switch( inst->Instruction.Saturate ) {
case TGSI_SAT_NONE:
&bld->exec_mask, pred);
}
else {
- LLVMValueRef temp_ptr = lp_get_temp_ptr_soa(bld, reg->Register.Index,
- chan_index);
+ LLVMValueRef temp_ptr;
+
+ switch (dtype) {
+ case TGSI_TYPE_UNSIGNED:
+ case TGSI_TYPE_SIGNED: {
+ LLVMTypeRef itype = LLVMVectorType(LLVMInt32TypeInContext(gallivm->context), 4);
+ LLVMTypeRef ivtype = LLVMPointerType(itype, 0);
+ LLVMValueRef tint_ptr = lp_get_temp_ptr_soa(bld, reg->Register.Index,
+ chan_index);
+ LLVMValueRef temp_value_ptr;
+
+ temp_ptr = LLVMBuildBitCast(builder, tint_ptr, ivtype, "");
+ temp_value_ptr = LLVMBuildBitCast(builder, value, itype, "");
+ value = temp_value_ptr;
+ break;
+ }
+ default:
+ case TGSI_TYPE_FLOAT:
+ case TGSI_TYPE_UNTYPED:
+ temp_ptr = lp_get_temp_ptr_soa(bld, reg->Register.Index,
+ chan_index);
+ break;
+ }
+
lp_exec_mask_store(&bld->exec_mask, bld_store, pred, value, temp_ptr);
}
break;
case TGSI_FILE_ADDRESS:
assert(idx < LP_MAX_TGSI_ADDRS);
for (i = 0; i < TGSI_NUM_CHANNELS; i++)
- bld->addr[idx][i] = lp_build_alloca(gallivm, vec_type, "addr");
+ bld->addr[idx][i] = lp_build_alloca(gallivm, bld_base->base.int_vec_type, "addr");
break;
case TGSI_FILE_PREDICATE: