i965: Apply the miptree offset to surface state for renderbuffers

Previously, we were completely ignoring the mt->offset field for
renderbuffers.  While it does have some alignment constraints, it is valid
to use it.  This patch adds the code to each of the 4 surface state setup
functions to handle it.

Reviewed-by: Neil Roberts <neil@linux.intel.com>

diff --git a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
index 85a08d55232bef735d96ef13e49ee9065aa83b2e..bf7936caac390a70b987c9162faa5aae4efe1051 100644 (file)
--- a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
+++ b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
@@ -658,8 +658,9 @@ brw_update_renderbuffer_surface(struct brw_context *brw,
              format << BRW_SURFACE_FORMAT_SHIFT);
 
    /* reloc */
+   assert(mt->offset % mt->cpp == 0);
    surf[1] = (intel_renderbuffer_get_tile_offsets(irb, &tile_x, &tile_y) +
-             mt->bo->offset64);
+             mt->bo->offset64 + mt->offset);
 
    surf[2] = ((rb->Width - 1) << BRW_SURFACE_WIDTH_SHIFT |
              (rb->Height - 1) << BRW_SURFACE_HEIGHT_SHIFT);

diff --git a/src/mesa/drivers/dri/i965/gen6_surface_state.c b/src/mesa/drivers/dri/i965/gen6_surface_state.c
index 27b441956df00e7813af1f2063aec213d2cd47c6..080e0f348fab886c9f3774024a0a7e0c7133e191 100644 (file)
--- a/src/mesa/drivers/dri/i965/gen6_surface_state.c
+++ b/src/mesa/drivers/dri/i965/gen6_surface_state.c
@@ -97,7 +97,8 @@ gen6_update_renderbuffer_surface(struct brw_context *brw,
              SET_FIELD(format, BRW_SURFACE_FORMAT);
 
    /* reloc */
-   surf[1] = mt->bo->offset64;
+   assert(mt->offset % mt->cpp == 0);
+   surf[1] = mt->bo->offset64 + mt->offset;
 
    /* In the gen6 PRM Volume 1 Part 1: Graphics Core, Section 7.18.3.7.1
     * (Surface Arrays For all surfaces other than separate stencil buffer):

diff --git a/src/mesa/drivers/dri/i965/gen7_wm_surface_state.c b/src/mesa/drivers/dri/i965/gen7_wm_surface_state.c
index e2c347a51eef9e41160c7f9d880fcd8b9fcebaaf..68f81d9a6cad57af855d342aa5b4cab65d1b7b20 100644 (file)
--- a/src/mesa/drivers/dri/i965/gen7_wm_surface_state.c
+++ b/src/mesa/drivers/dri/i965/gen7_wm_surface_state.c
@@ -517,7 +517,8 @@ gen7_update_renderbuffer_surface(struct brw_context *brw,
       surf[0] |= GEN7_SURFACE_IS_ARRAY;
    }
 
-   surf[1] = mt->bo->offset64;
+   assert(mt->offset % mt->cpp == 0);
+   surf[1] = mt->bo->offset64 + mt->offset;
 
    assert(brw->has_surface_tile_offset);
 

diff --git a/src/mesa/drivers/dri/i965/gen8_surface_state.c b/src/mesa/drivers/dri/i965/gen8_surface_state.c
index d1b095cf53559eed1beed6b808fc38d1e0d99b55..45c35db0a4d006b38178fb8bcc076d3028b99fd1 100644 (file)
--- a/src/mesa/drivers/dri/i965/gen8_surface_state.c
+++ b/src/mesa/drivers/dri/i965/gen8_surface_state.c
@@ -432,7 +432,8 @@ gen8_update_renderbuffer_surface(struct brw_context *brw,
              SET_FIELD(HSW_SCS_BLUE,  GEN7_SURFACE_SCS_B) |
              SET_FIELD(HSW_SCS_ALPHA, GEN7_SURFACE_SCS_A);
 
-   *((uint64_t *) &surf[8]) = mt->bo->offset64; /* reloc */
+   assert(mt->offset % mt->cpp == 0);
+   *((uint64_t *) &surf[8]) = mt->bo->offset64 + mt->offset; /* reloc */
 
    if (aux_mt) {
       *((uint64_t *) &surf[10]) = aux_mt->bo->offset64;