Update working and completed bugs

diff --git a/veera.mdwn b/veera.mdwn
index 8ae18aa011b0021eac078f36cd8122b38287e3e7..cbb3a0587d0c9fe9511ddd1158582ef7e68e213e 100644 (file)
--- a/veera.mdwn
+++ b/veera.mdwn
@@ -8,22 +8,31 @@ Helping Core Hardware developers.
 
 ## Currently working on
 
-### NLNet.2019.10.Formal
+### NLNet.2019.10.032.Formal
 
-* [Bug #838](https://bugs.libre-soc.org/show_bug.cgi?id=838):
-  sync or at least statically check fields.text, power_decoder, trans/svp64, CSVs between each other
+* [Bug #883](https://bugs.libre-soc.org/show_bug.cgi?id=883):
+  add cvc5 and bitwuzla to hdl-yosys-tools
+
+## Currently deffered
+
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=602> Low performance bare minimum functionality SIMD emulator required
+
+## Completed but not yet submitted:
+
+### NLNet.2019.10.046.Standards
 
 * [Bug #839](https://bugs.libre-soc.org/show_bug.cgi?id=839):
   SVP64 / Extra-V / ZOLC whitepaper
 
+### NLNet.2019.10.032.Formal
+
 * [Bug #847](https://bugs.libre-soc.org/show_bug.cgi?id=847):
   dev\-env\-setup script for binutils-gdb for target powerpc64le\-linux\-gnu
 
-## Currently deffered
-
- - <https://bugs.libre-soc.org/show_bug.cgi?id=602> Low performance bare minimum functionality SIMD emulator required
+### NLNet.2019.10.043.Wishbone
 
-## Completed but not yet submitted:
+* [Bug #878](https://bugs.libre-soc.org/show_bug.cgi?id=878):
+  image conversion explaining multi-issue
 
 ## Submitted for NLNet RFP