Remove YS_ATTRIBUTE(unused) where present just for log_assert()/log_debug().

diff --git a/frontends/aiger/aigerparse.cc b/frontends/aiger/aigerparse.cc
index 9d967e6fc41ac08698474be9e94d52344de7fea7..07e3cd6e0aad0eb7672dec50ede179e8753d8070 100644 (file)
--- a/frontends/aiger/aigerparse.cc
+++ b/frontends/aiger/aigerparse.cc
@@ -69,7 +69,7 @@ struct ConstEvalAig
                                continue;
                        for (auto &it2 : it.second->connections())
                                if (yosys_celltypes.cell_output(it.second->type, it2.first)) {
-                                       auto r YS_ATTRIBUTE(unused) = sig2driver.insert(std::make_pair(it2.second, it.second));
+                                       auto r = sig2driver.insert(std::make_pair(it2.second, it.second));
                                        log_assert(r.second);
                                }
                }
@@ -400,9 +400,9 @@ void AigerReader::parse_xaiger()
        for (int c = f.get(); c != EOF; c = f.get()) {
                // XAIGER extensions
                if (c == 'm') {
-                       uint32_t dataSize YS_ATTRIBUTE(unused) = parse_xaiger_literal(f);
+                       uint32_t dataSize = parse_xaiger_literal(f);
                        uint32_t lutNum = parse_xaiger_literal(f);
-                       uint32_t lutSize YS_ATTRIBUTE(unused) = parse_xaiger_literal(f);
+                       uint32_t lutSize = parse_xaiger_literal(f);
                        log_debug("m: dataSize=%u lutNum=%u lutSize=%u\n", dataSize, lutNum, lutSize);
                        ConstEvalAig ce(module);
                        for (unsigned i = 0; i < lutNum; ++i) {
@@ -434,7 +434,7 @@ void AigerReader::parse_xaiger()
                                        int gray = j ^ (j >> 1);
                                        ce.set_incremental(input_sig, RTLIL::Const{gray, GetSize(input_sig)});
                                        RTLIL::SigBit o(output_sig);
-                                       bool success YS_ATTRIBUTE(unused) = ce.eval(o);
+                                       bool success = ce.eval(o);
                                        log_assert(success);
                                        log_assert(o.wire == nullptr);
                                        lut_mask[gray] = o.data;
@@ -446,7 +446,7 @@ void AigerReader::parse_xaiger()
                        }
                }
                else if (c == 'r') {
-                       uint32_t dataSize YS_ATTRIBUTE(unused) = parse_xaiger_literal(f);
+                       uint32_t dataSize = parse_xaiger_literal(f);
                        flopNum = parse_xaiger_literal(f);
                        log_debug("flopNum = %u\n", flopNum);
                        log_assert(dataSize == (flopNum+1) * sizeof(uint32_t));
@@ -455,7 +455,7 @@ void AigerReader::parse_xaiger()
                                mergeability.emplace_back(parse_xaiger_literal(f));
                }
                else if (c == 's') {
-                       uint32_t dataSize YS_ATTRIBUTE(unused) = parse_xaiger_literal(f);
+                       uint32_t dataSize = parse_xaiger_literal(f);
                        flopNum = parse_xaiger_literal(f);
                        log_assert(dataSize == (flopNum+1) * sizeof(uint32_t));
                        initial_state.reserve(flopNum);
@@ -469,15 +469,15 @@ void AigerReader::parse_xaiger()
                }
                else if (c == 'h') {
                        f.ignore(sizeof(uint32_t));
-                       uint32_t version YS_ATTRIBUTE(unused) = parse_xaiger_literal(f);
+                       uint32_t version = parse_xaiger_literal(f);
                        log_assert(version == 1);
-                       uint32_t ciNum YS_ATTRIBUTE(unused) = parse_xaiger_literal(f);
+                       uint32_t ciNum = parse_xaiger_literal(f);
                        log_debug("ciNum = %u\n", ciNum);
-                       uint32_t coNum YS_ATTRIBUTE(unused) = parse_xaiger_literal(f);
+                       uint32_t coNum = parse_xaiger_literal(f);
                        log_debug("coNum = %u\n", coNum);
                        piNum = parse_xaiger_literal(f);
                        log_debug("piNum = %u\n", piNum);
-                       uint32_t poNum YS_ATTRIBUTE(unused) = parse_xaiger_literal(f);
+                       uint32_t poNum = parse_xaiger_literal(f);
                        log_debug("poNum = %u\n", poNum);
                        uint32_t boxNum = parse_xaiger_literal(f);
                        log_debug("boxNum = %u\n", boxNum);

diff --git a/frontends/ast/simplify.cc b/frontends/ast/simplify.cc
index 5f026dfed890f2dad0f1ff4b29b30ba839417381..55e7da0aa88669e99b99612ce0fe2977aa8f4e55 100644 (file)
--- a/frontends/ast/simplify.cc
+++ b/frontends/ast/simplify.cc
@@ -778,7 +778,7 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage,
                                while (node->simplify(true, false, false, 1, -1, false, node->type == AST_PARAMETER || node->type == AST_LOCALPARAM))
                                        did_something = true;
                        if (node->type == AST_ENUM) {
-                               for (auto enode YS_ATTRIBUTE(unused) : node->children){
+                               for (auto enode : node->children){
                                        log_assert(enode->type==AST_ENUM_ITEM);
                                        while (node->simplify(true, false, false, 1, -1, false, in_param))
                                                did_something = true;

diff --git a/frontends/verific/verific.cc b/frontends/verific/verific.cc
index 1630c57bca91760e7032907d6381cebfcb754ab2..68d473726ca38f992f8ec3940d8b94a127ea64a1 100644 (file)
--- a/frontends/verific/verific.cc
+++ b/frontends/verific/verific.cc
@@ -1882,7 +1882,7 @@ struct VerificExtNets
                                new_net = new Net(name.c_str());
                                nl->Add(new_net);
 
-                               Net *n YS_ATTRIBUTE(unused) = route_up(new_net, port->IsOutput(), ca_nl, ca_net);
+                               Net *n = route_up(new_net, port->IsOutput(), ca_nl, ca_net);
                                log_assert(n == ca_net);
                        }
 

diff --git a/kernel/log.h b/kernel/log.h
index 9935a9271a06d7e59070bd2cb96fae974dee2946..e9d09d0dab1a71d0dfb4b6d4d9bcf175e010e8ff 100644 (file)
--- a/kernel/log.h
+++ b/kernel/log.h
@@ -370,7 +370,7 @@ static inline void log_dump_val_worker(char *v) { log("%s", v); }
 static inline void log_dump_val_worker(const char *v) { log("%s", v); }
 static inline void log_dump_val_worker(std::string v) { log("%s", v.c_str()); }
 static inline void log_dump_val_worker(PerformanceTimer p) { log("%f seconds", p.sec()); }
-static inline void log_dump_args_worker(const char *p YS_ATTRIBUTE(unused)) { log_assert(*p == 0); }
+static inline void log_dump_args_worker(const char *p) { log_assert(*p == 0); }
 void log_dump_val_worker(RTLIL::IdString v);
 void log_dump_val_worker(RTLIL::SigSpec v);
 void log_dump_val_worker(RTLIL::State v);

diff --git a/kernel/modtools.h b/kernel/modtools.h
index 9d6a5050276ef1e80a4e04a111ac9140877a7836..29c510059ffc4f5e0220ffdeb6e9bea8eacffe0d 100644 (file)
--- a/kernel/modtools.h
+++ b/kernel/modtools.h
@@ -169,7 +169,7 @@ struct ModIndex : public RTLIL::Monitor
                port_add(cell, port, sig);
        }
 
-       void notify_connect(RTLIL::Module *mod YS_ATTRIBUTE(unused), const RTLIL::SigSig &sigsig) override
+       void notify_connect(RTLIL::Module *mod, const RTLIL::SigSig &sigsig) override
        {
                log_assert(module == mod);
 
@@ -214,13 +214,13 @@ struct ModIndex : public RTLIL::Monitor
                }
        }
 
-       void notify_connect(RTLIL::Module *mod YS_ATTRIBUTE(unused), const std::vector<RTLIL::SigSig>&) override
+       void notify_connect(RTLIL::Module *mod, const std::vector<RTLIL::SigSig>&) override
        {
                log_assert(module == mod);
                auto_reload_module = true;
        }
 
-       void notify_blackout(RTLIL::Module *mod YS_ATTRIBUTE(unused)) override
+       void notify_blackout(RTLIL::Module *mod) override
        {
                log_assert(module == mod);
                auto_reload_module = true;

diff --git a/passes/opt/opt_expr.cc b/passes/opt/opt_expr.cc
index c16f22b388954608504e29a610feb884ddf075f3..5c224d4bb85809b31431ba25cddb60af795c52c7 100644 (file)
--- a/passes/opt/opt_expr.cc
+++ b/passes/opt/opt_expr.cc
@@ -117,7 +117,7 @@ void replace_undriven(RTLIL::Module *module, const CellTypes &ct)
 }
 
 void replace_cell(SigMap &assign_map, RTLIL::Module *module, RTLIL::Cell *cell,
-               const std::string &info YS_ATTRIBUTE(unused), IdString out_port, RTLIL::SigSpec out_val)
+               const std::string &info, IdString out_port, RTLIL::SigSpec out_val)
 {
        RTLIL::SigSpec Y = cell->getPort(out_port);
        out_val.extend_u0(Y.size(), false);

diff --git a/passes/techmap/abc9_ops.cc b/passes/techmap/abc9_ops.cc
index 9b69538e32a95f8fcbf8b861896f1f2bc78d7cd9..98d0207c4cecfe72381d2ef6661798143c29fbc5 100644 (file)
--- a/passes/techmap/abc9_ops.cc
+++ b/passes/techmap/abc9_ops.cc
@@ -741,7 +741,7 @@ void prep_xaiger(RTLIL::Module *module, bool dff)
        if (ys_debug(1))
                toposort.analyze_loops = true;
 
-       bool no_loops YS_ATTRIBUTE(unused) = toposort.sort();
+       bool no_loops = toposort.sort();
 
        if (ys_debug(1)) {
                unsigned i = 0;
@@ -1453,7 +1453,7 @@ void reintegrate(RTLIL::Module *module, bool dff_mode)
                        for (auto driver_cell : bit_drivers.at(it.first))
                        for (auto user_cell : it.second)
                                toposort.edge(driver_cell, user_cell);
-       bool no_loops YS_ATTRIBUTE(unused) = toposort.sort();
+       bool no_loops = toposort.sort();
        log_assert(no_loops);
 
        for (auto ii = toposort.sorted.rbegin(); ii != toposort.sorted.rend(); ii++) {

diff --git a/passes/techmap/dfflibmap.cc b/passes/techmap/dfflibmap.cc
index 6d1eaa7f8d67bc0c1bd92bb9bcd3c66b44967b1c..c189d649b68bd972e63b8427d9f8a39672e5865a 100644 (file)
--- a/passes/techmap/dfflibmap.cc
+++ b/passes/techmap/dfflibmap.cc
@@ -409,11 +409,11 @@ static void map_sr_to_arst(IdString from, IdString to)
        if (!cell_mappings.count(from) || cell_mappings.count(to) > 0)
                return;
 
-       char from_clk_pol YS_ATTRIBUTE(unused) = from[8];
+       char from_clk_pol = from[8];
        char from_set_pol = from[9];
        char from_clr_pol = from[10];
-       char to_clk_pol YS_ATTRIBUTE(unused) = to[6];
-       char to_rst_pol YS_ATTRIBUTE(unused) = to[7];
+       char to_clk_pol = to[6];
+       char to_rst_pol = to[7];
        char to_rst_val = to[8];
 
        log_assert(from_clk_pol == to_clk_pol);
@@ -455,9 +455,9 @@ static void map_adff_to_dff(IdString from, IdString to)
        if (!cell_mappings.count(from) || cell_mappings.count(to) > 0)
                return;
 
-       char from_clk_pol YS_ATTRIBUTE(unused) = from[6];
+       char from_clk_pol = from[6];
        char from_rst_pol = from[7];
-       char to_clk_pol YS_ATTRIBUTE(unused) = to[6];
+       char to_clk_pol = to[6];
 
        log_assert(from_clk_pol == to_clk_pol);
 

diff --git a/passes/tests/test_abcloop.cc b/passes/tests/test_abcloop.cc
index a7d51293d0ba378ff20a3f67f5afb33c841dc59d..2d80e66e45467b8947c52bba07df3fa2a6b8e442 100644 (file)
--- a/passes/tests/test_abcloop.cc
+++ b/passes/tests/test_abcloop.cc
@@ -132,7 +132,7 @@ static void test_abcloop()
                SatGen satgen(ez.get(), &sigmap);
 
                for (auto c : module->cells()) {
-                       bool ok YS_ATTRIBUTE(unused) = satgen.importCell(c);
+                       bool ok = satgen.importCell(c);
                        log_assert(ok);
                }
 
@@ -182,7 +182,7 @@ static void test_abcloop()
        SatGen satgen(ez.get(), &sigmap);
 
        for (auto c : module->cells()) {
-               bool ok YS_ATTRIBUTE(unused) = satgen.importCell(c);
+               bool ok = satgen.importCell(c);
                log_assert(ok);
        }