sparc.md (movsf_const_intreg): Add constraints for regclass' sake.

	* config/sparc/sparc.md (movsf_const_intreg): Add constraints for
	regclass' sake.
	(movdf_const_intreg_sp32): Likewise. Prefer the memory load
	alternative because setting up 64bit constant is usually costly,
	especially when reload is in progress or completed.
	(movdf_const_intreg_sp64): Likewise.
	(movdf_const_intreg split): Fix building up constants when
	HOST_BITS_PER_WIDE_INT is 64 yet long is 32bit.

From-SVN: r30750

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index deb8060e40e964ba50ab253fd5a49f23a3a76e50..0737719128a03fbe4c64f771c262582b57aaf953 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,14 @@
+1999-12-01  Jakub Jelinek  <jakub@redhat.com>
+
+       * config/sparc/sparc.md (movsf_const_intreg): Add constraints for
+       regclass' sake.
+       (movdf_const_intreg_sp32): Likewise. Prefer the memory load
+       alternative because setting up 64bit constant is usually costly,
+       especially when reload is in progress or completed.
+       (movdf_const_intreg_sp64): Likewise.
+       (movdf_const_intreg split): Fix building up constants when
+       HOST_BITS_PER_WIDE_INT is 64 yet long is 32bit.
+
 Wed Dec  1 16:51:22 1999  Jeffrey A Law  (law@cygnus.com)
 
        * combine.c (if_then_else_cond): Use const_true_rtx instead of

diff --git a/gcc/config/sparc/sparc.md b/gcc/config/sparc/sparc.md
index 95c686852273a623eabd1282c6f498463a5a1778..1dcbf35499eb8d8b87827c50bf20fc90f19e94e2 100644 (file)
--- a/gcc/config/sparc/sparc.md
+++ b/gcc/config/sparc/sparc.md
@@ -2765,7 +2765,7 @@
 
 (define_insn "*movsf_const_intreg"
   [(set (match_operand:SF 0 "register_operand" "=f,r")
-        (match_operand:SF 1 "const_double_operand" "m,F"))]
+        (match_operand:SF 1 "const_double_operand" "m#F,F"))]
   "TARGET_FPU"
   "*
 {
@@ -2932,8 +2932,8 @@
    (set_attr "length" "1")])
 
 (define_insn "*movdf_const_intreg_sp32"
-  [(set (match_operand:DF 0 "register_operand" "=e,e,r")
-        (match_operand:DF 1 "const_double_operand" "T,o,F"))]
+  [(set (match_operand:DF 0 "register_operand" "=e,e,?r")
+        (match_operand:DF 1 "const_double_operand" "T#F,o#F,F"))]
   "TARGET_FPU && ! TARGET_ARCH64"
   "@
    ldd\\t%1, %0
@@ -2945,8 +2945,8 @@
 ;; Now that we redo life analysis with a clean slate after
 ;; instruction splitting for sched2 this can work.
 (define_insn "*movdf_const_intreg_sp64"
-  [(set (match_operand:DF 0 "register_operand" "=e,r")
-        (match_operand:DF 1 "const_double_operand" "m,F"))]
+  [(set (match_operand:DF 0 "register_operand" "=e,?r")
+        (match_operand:DF 1 "const_double_operand" "m#F,F"))]
   "TARGET_FPU && TARGET_ARCH64"
   "@
    ldd\\t%1, %0
@@ -2978,8 +2978,8 @@
 #if HOST_BITS_PER_WIDE_INT == 64
       HOST_WIDE_INT val;
 
-      val = ((HOST_WIDE_INT)l[1] |
-             ((HOST_WIDE_INT)l[0] << 32));
+      val = ((HOST_WIDE_INT)(unsigned long)l[1] |
+             ((HOST_WIDE_INT)(unsigned long)l[0] << 32));
       emit_insn (gen_movdi (operands[0], GEN_INT (val)));
 #else
       emit_insn (gen_movdi (operands[0],