RISC-V: Add macro for ilp32e ABI. Cleanup white space.

	gcc/
	* config/riscv/riscv-c.c (riscv_cpu_cpp_builtins): For ABI_ILP32E,
	also define __riscv_abi_rve.  Delete trailing white space.

From-SVN: r264821

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 6bec9842ae8e7a05cda8da60bd4566e2810164e5..8e7cb548c152ece70df1c92736f4a88d3025f594 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,8 @@
+2018-10-03  Jim Wilson  <jimw@sifive.com>
+
+       * config/riscv/riscv-c.c (riscv_cpu_cpp_builtins): For ABI_ILP32E,
+       also define __riscv_abi_rve.  Delete trailing white space.
+
 2018-10-03  Paul Koning  <ni1d@arrl.net>
 
        Enable LRA register allocator for PDP11.

diff --git a/gcc/config/riscv/riscv-c.c b/gcc/config/riscv/riscv-c.c
index 513f974d9aa2465062ed2f8cf8965bbaecd41bc0..d3ecd0796e8bad6108733c7cad441baa9ee9446c 100644 (file)
--- a/gcc/config/riscv/riscv-c.c
+++ b/gcc/config/riscv/riscv-c.c
@@ -35,62 +35,65 @@ void
 riscv_cpu_cpp_builtins (cpp_reader *pfile)
 {
   builtin_define ("__riscv");
-  
+
   if (TARGET_RVC)
     builtin_define ("__riscv_compressed");
-  
+
   if (TARGET_RVE)
     builtin_define ("__riscv_32e");
 
   if (TARGET_ATOMIC)
     builtin_define ("__riscv_atomic");
-  
+
   if (TARGET_MUL)
     builtin_define ("__riscv_mul");
   if (TARGET_DIV)
     builtin_define ("__riscv_div");
   if (TARGET_DIV && TARGET_MUL)
     builtin_define ("__riscv_muldiv");
-  
+
   builtin_define_with_int_value ("__riscv_xlen", UNITS_PER_WORD * 8);
   if (TARGET_HARD_FLOAT)
     builtin_define_with_int_value ("__riscv_flen", UNITS_PER_FP_REG * 8);
-  
+
   if (TARGET_HARD_FLOAT && TARGET_FDIV)
     {
       builtin_define ("__riscv_fdiv");
       builtin_define ("__riscv_fsqrt");
     }
-  
+
   switch (riscv_abi)
     {
-    case ABI_ILP32:
     case ABI_ILP32E:
+      builtin_define ("__riscv_abi_rve");
+      gcc_fallthrough ();
+
+    case ABI_ILP32:
     case ABI_LP64:
       builtin_define ("__riscv_float_abi_soft");
       break;
-  
+
     case ABI_ILP32F:
     case ABI_LP64F:
       builtin_define ("__riscv_float_abi_single");
       break;
-  
+
     case ABI_ILP32D:
     case ABI_LP64D:
       builtin_define ("__riscv_float_abi_double");
       break;
     }
-  
+
   switch (riscv_cmodel)
     {
     case CM_MEDLOW:
       builtin_define ("__riscv_cmodel_medlow");
       break;
-  
+
     case CM_MEDANY:
       builtin_define ("__riscv_cmodel_medany");
       break;
-  
+
     case CM_PIC:
       builtin_define ("__riscv_cmodel_pic");
       break;