Add support for new FF types in some opt passes.

diff --git a/passes/opt/opt_expr.cc b/passes/opt/opt_expr.cc
index c16f22b388954608504e29a610feb884ddf075f3..170afb19cee869171f3ec04167c42fe64fe81dcd 100644 (file)
--- a/passes/opt/opt_expr.cc
+++ b/passes/opt/opt_expr.cc
@@ -467,15 +467,21 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
 
                if (clkinv)
                {
-                       if (cell->type.in(ID($dff), ID($dffe), ID($dffsr), ID($adff), ID($fsm), ID($memrd), ID($memwr)))
+                       if (cell->type.in(ID($dff), ID($dffe), ID($dffsr), ID($dffsre), ID($adff), ID($adffe), ID($sdff), ID($sdffe), ID($sdffce), ID($fsm), ID($memrd), ID($memwr)))
                                handle_polarity_inv(cell, ID::CLK, ID::CLK_POLARITY, assign_map, invert_map);
 
-                       if (cell->type.in(ID($sr), ID($dffsr), ID($dlatchsr))) {
+                       if (cell->type.in(ID($sr), ID($dffsr), ID($dffsre), ID($dlatchsr))) {
                                handle_polarity_inv(cell, ID::SET, ID::SET_POLARITY, assign_map, invert_map);
                                handle_polarity_inv(cell, ID::CLR, ID::CLR_POLARITY, assign_map, invert_map);
                        }
 
-                       if (cell->type.in(ID($dffe), ID($dlatch), ID($dlatchsr)))
+                       if (cell->type.in(ID($adff), ID($adffe), ID($adlatch)))
+                               handle_polarity_inv(cell, ID::ARST, ID::ARST_POLARITY, assign_map, invert_map);
+
+                       if (cell->type.in(ID($sdff), ID($sdffe), ID($sdffce)))
+                               handle_polarity_inv(cell, ID::SRST, ID::SRST_POLARITY, assign_map, invert_map);
+
+                       if (cell->type.in(ID($dffe), ID($adffe), ID($sdffe), ID($sdffce), ID($dffsre), ID($dlatch), ID($adlatch), ID($dlatchsr)))
                                handle_polarity_inv(cell, ID::EN, ID::EN_POLARITY, assign_map, invert_map);
 
                        handle_clkpol_celltype_swap(cell, "$_SR_N?_", "$_SR_P?_", ID::S, assign_map, invert_map);
@@ -489,12 +495,35 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
                        handle_clkpol_celltype_swap(cell, "$_DFF_N??_", "$_DFF_P??_", ID::C, assign_map, invert_map);
                        handle_clkpol_celltype_swap(cell, "$_DFF_?N?_", "$_DFF_?P?_", ID::R, assign_map, invert_map);
 
+                       handle_clkpol_celltype_swap(cell, "$_DFFE_N???_", "$_DFFE_P???_", ID::C, assign_map, invert_map);
+                       handle_clkpol_celltype_swap(cell, "$_DFFE_?N??_", "$_DFFE_?P??_", ID::R, assign_map, invert_map);
+                       handle_clkpol_celltype_swap(cell, "$_DFFE_???N_", "$_DFFE_???P_", ID::E, assign_map, invert_map);
+
+                       handle_clkpol_celltype_swap(cell, "$_SDFF_N??_", "$_SDFF_P??_", ID::C, assign_map, invert_map);
+                       handle_clkpol_celltype_swap(cell, "$_SDFF_?N?_", "$_SDFF_?P?_", ID::R, assign_map, invert_map);
+
+                       handle_clkpol_celltype_swap(cell, "$_SDFFE_N???_", "$_SDFFE_P???_", ID::C, assign_map, invert_map);
+                       handle_clkpol_celltype_swap(cell, "$_SDFFE_?N??_", "$_SDFFE_?P??_", ID::R, assign_map, invert_map);
+                       handle_clkpol_celltype_swap(cell, "$_SDFFE_???N_", "$_SDFFE_???P_", ID::E, assign_map, invert_map);
+
+                       handle_clkpol_celltype_swap(cell, "$_SDFFCE_N???_", "$_SDFFCE_P???_", ID::C, assign_map, invert_map);
+                       handle_clkpol_celltype_swap(cell, "$_SDFFCE_?N??_", "$_SDFFCE_?P??_", ID::R, assign_map, invert_map);
+                       handle_clkpol_celltype_swap(cell, "$_SDFFCE_???N_", "$_SDFFCE_???P_", ID::E, assign_map, invert_map);
+
                        handle_clkpol_celltype_swap(cell, "$_DFFSR_N??_", "$_DFFSR_P??_", ID::C, assign_map, invert_map);
                        handle_clkpol_celltype_swap(cell, "$_DFFSR_?N?_", "$_DFFSR_?P?_", ID::S, assign_map, invert_map);
                        handle_clkpol_celltype_swap(cell, "$_DFFSR_??N_", "$_DFFSR_??P_", ID::R, assign_map, invert_map);
 
+                       handle_clkpol_celltype_swap(cell, "$_DFFSRE_N???_", "$_DFFSRE_P???_", ID::C, assign_map, invert_map);
+                       handle_clkpol_celltype_swap(cell, "$_DFFSRE_?N??_", "$_DFFSRE_?P??_", ID::S, assign_map, invert_map);
+                       handle_clkpol_celltype_swap(cell, "$_DFFSRE_??N?_", "$_DFFSRE_??P?_", ID::R, assign_map, invert_map);
+                       handle_clkpol_celltype_swap(cell, "$_DFFSRE_???N_", "$_DFFSRE_???P_", ID::E, assign_map, invert_map);
+
                        handle_clkpol_celltype_swap(cell, "$_DLATCH_N_", "$_DLATCH_P_", ID::E, assign_map, invert_map);
 
+                       handle_clkpol_celltype_swap(cell, "$_DLATCH_N??_", "$_DLATCH_P??_", ID::E, assign_map, invert_map);
+                       handle_clkpol_celltype_swap(cell, "$_DLATCH_?N?_", "$_DLATCH_?P?_", ID::R, assign_map, invert_map);
+
                        handle_clkpol_celltype_swap(cell, "$_DLATCHSR_N??_", "$_DLATCHSR_P??_", ID::E, assign_map, invert_map);
                        handle_clkpol_celltype_swap(cell, "$_DLATCHSR_?N?_", "$_DLATCHSR_?P?_", ID::S, assign_map, invert_map);
                        handle_clkpol_celltype_swap(cell, "$_DLATCHSR_??N_", "$_DLATCHSR_??P_", ID::R, assign_map, invert_map);

diff --git a/passes/opt/pmux2shiftx.cc b/passes/opt/pmux2shiftx.cc
index 9a00f84b9e67eb48a33793d489db31f683fabfe2..9f226e12dbc02863b5acbe088d2ec47822122779 100644 (file)
--- a/passes/opt/pmux2shiftx.cc
+++ b/passes/opt/pmux2shiftx.cc
@@ -63,11 +63,13 @@ struct OnehotDatabase
                        vector<SigSpec> inputs;
                        SigSpec output;
 
-                       if (cell->type.in(ID($adff), ID($dff), ID($dffe), ID($dlatch), ID($ff)))
+                       if (cell->type.in(ID($adff), ID($adffe), ID($dff), ID($dffe), ID($sdff), ID($sdffe), ID($sdffce), ID($dlatch), ID($adlatch), ID($ff)))
                        {
                                output = cell->getPort(ID::Q);
-                               if (cell->type == ID($adff))
+                               if (cell->type.in(ID($adff), ID($adffe), ID($adlatch)))
                                        inputs.push_back(cell->getParam(ID::ARST_VALUE));
+                               if (cell->type.in(ID($sdff), ID($sdffe), ID($sdffce)))
+                                       inputs.push_back(cell->getParam(ID::SRST_VALUE));
                                inputs.push_back(cell->getPort(ID::D));
                        }
 

diff --git a/passes/opt/wreduce.cc b/passes/opt/wreduce.cc
index 8ce2fd478c2f1549821544a604f05421760a2780..78e2bcbea6dd9d8ca5ea77cda284f9f92bf6973e 100644 (file)
--- a/passes/opt/wreduce.cc
+++ b/passes/opt/wreduce.cc
@@ -39,7 +39,8 @@ struct WreduceConfig
                        ID($lt), ID($le), ID($eq), ID($ne), ID($eqx), ID($nex), ID($ge), ID($gt),
                        ID($add), ID($sub), ID($mul), // ID($div), ID($mod), ID($divfloor), ID($modfloor), ID($pow),
                        ID($mux), ID($pmux),
-                       ID($dff), ID($adff)
+                       ID($dff), ID($dffe), ID($adff), ID($adffe), ID($sdff), ID($sdffe), ID($sdffce),
+                       ID($dlatch), ID($adlatch),
                });
        }
 };
@@ -143,8 +144,8 @@ struct WreduceWorker
 
                SigSpec sig_d = mi.sigmap(cell->getPort(ID::D));
                SigSpec sig_q = mi.sigmap(cell->getPort(ID::Q));
-               bool is_adff = (cell->type == ID($adff));
-               Const initval, arst_value;
+               bool has_reset = false;
+               Const initval, rst_value;
 
                int width_before = GetSize(sig_q);
 
@@ -152,7 +153,11 @@ struct WreduceWorker
                        return;
 
                if (cell->parameters.count(ID::ARST_VALUE)) {
-                       arst_value = cell->parameters[ID::ARST_VALUE];
+                       rst_value = cell->parameters[ID::ARST_VALUE];
+                       has_reset = true;
+               } else if (cell->parameters.count(ID::SRST_VALUE)) {
+                       rst_value = cell->parameters[ID::SRST_VALUE];
+                       has_reset = true;
                }
 
                bool zero_ext = sig_d[GetSize(sig_d)-1] == State::S0;
@@ -169,7 +174,7 @@ struct WreduceWorker
                for (int i = GetSize(sig_q)-1; i >= 0; i--)
                {
                        if (zero_ext && sig_d[i] == State::S0 && (initval[i] == State::S0 || initval[i] == State::Sx) &&
-                                       (!is_adff || i >= GetSize(arst_value) || arst_value[i] == State::S0 || arst_value[i] == State::Sx)) {
+                                       (!has_reset || i >= GetSize(rst_value) || rst_value[i] == State::S0 || rst_value[i] == State::Sx)) {
                                module->connect(sig_q[i], State::S0);
                                remove_init_bits.insert(sig_q[i]);
                                sig_d.remove(i);
@@ -178,7 +183,7 @@ struct WreduceWorker
                        }
 
                        if (sign_ext && i > 0 && sig_d[i] == sig_d[i-1] && initval[i] == initval[i-1] &&
-                                       (!is_adff || i >= GetSize(arst_value) || arst_value[i] == arst_value[i-1])) {
+                                       (!has_reset || i >= GetSize(rst_value) || rst_value[i] == rst_value[i-1])) {
                                module->connect(sig_q[i], sig_q[i-1]);
                                remove_init_bits.insert(sig_q[i]);
                                sig_d.remove(i);
@@ -221,8 +226,11 @@ struct WreduceWorker
 
                // Narrow ARST_VALUE parameter to new size.
                if (cell->parameters.count(ID::ARST_VALUE)) {
-                       arst_value.bits.resize(GetSize(sig_q));
-                       cell->setParam(ID::ARST_VALUE, arst_value);
+                       rst_value.bits.resize(GetSize(sig_q));
+                       cell->setParam(ID::ARST_VALUE, rst_value);
+               } else if (cell->parameters.count(ID::SRST_VALUE)) {
+                       rst_value.bits.resize(GetSize(sig_q));
+                       cell->setParam(ID::SRST_VALUE, rst_value);
                }
 
                cell->setPort(ID::D, sig_d);
@@ -272,7 +280,7 @@ struct WreduceWorker
                if (cell->type.in(ID($mux), ID($pmux)))
                        return run_cell_mux(cell);
 
-               if (cell->type.in(ID($dff), ID($adff)))
+               if (cell->type.in(ID($dff), ID($dffe), ID($adff), ID($adffe), ID($sdff), ID($sdffe), ID($sdffce), ID($dlatch), ID($adlatch)))
                        return run_cell_dff(cell);
 
                SigSpec sig = mi.sigmap(cell->getPort(ID::Y));