+2017-11-23 Julia Koval <julia.koval@intel.com>
+
+ config.gcc (avx512vbmi2intrin.h, avx512vbmi2vlintrin): New headers.
+ config/i386/avx512vbmi2intrin.h (_mm512_mask_compress_epi8,
+ _mm512_maskz_compress_epi8, _mm512_mask_compressstoreu_epi8,
+ _mm512_mask_compress_epi16, _mm512_maskz_compress_epi16,
+ _mm512_mask_compressstoreu_epi16): New.
+ config/i386/avx512vbmi2vlintrin.h (_mm_mask_compress_epi8,
+ _mm_maskz_compress_epi8, _mm256_mask_compressstoreu_epi16,
+ _mm_mask_compress_epi16, _mm_maskz_compress_epi16,
+ _mm256_mask_compress_epi16, _mm256_maskz_compress_epi16,
+ _mm_mask_compressstoreu_epi8, _mm_mask_compressstoreu_epi16,
+ _mm256_mask_compress_epi8, _mm256_maskz_compress_epi8,
+ _mm256_mask_compressstoreu_epi8): New.
+ config/i386/i386-builtin-types.def (VOID_FTYPE_PV64QI_V64QI_UDI,
+ VOID_FTYPE_PV32HI_V32HI_USI, VOID_FTYPE_PV32QI_V32QI_USI,
+ VOID_FTYPE_PV16QI_V16QI_UHI, VOID_FTYPE_PV16HI_V16HI_UHI,
+ VOID_FTYPE_PV8HI_V8HI_UQI): New types.
+ config/i386/i386-builtin.def (__builtin_ia32_compressqi512_mask,
+ __builtin_ia32_compresshi512_mask, __builtin_ia32_compressqi256_mask,
+ __builtin_ia32_compressqi128_mask, __builtin_ia32_compresshi256_mask,
+ __builtin_ia32_compresshi128_mask,
+ __builtin_ia32_compressstoreuqi512_mask,
+ __builtin_ia32_compressstoreuhi512_mask,
+ __builtin_ia32_compressstoreuqi256_mask,
+ __builtin_ia32_compressstoreuqi128_mask,
+ __builtin_ia32_compressstoreuhi256_mask,
+ __builtin_ia32_compressstoreuhi128_mask): New builtins.
+ config/i386/i386.c (ix86_init_mmx_sse_builtins): Create special args
+ array for flags2.
+ (ix86_expand_special_args_builtin): Handle new types.
+ (s4fma_expand): Handle new builtin array.
+ config/i386/immintrin.h: Include new headers.
+ config/i386/sse.md (VI12_AVX512VLBW): New iterator.
+ (compress<mode>_mask, compressstore<mode>_mask): New patterns.
+
2017-11-23 Jakub Jelinek <jakub@redhat.com>
* config/rs6000/rs6000.c (rs6000_gimple_fold_builtin): Formatting
--- /dev/null
+/* Copyright (C) 2013-2017 Free Software Foundation, Inc.
+
+ This file is part of GCC.
+
+ GCC is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3, or (at your option)
+ any later version.
+
+ GCC is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ Under Section 7 of GPL version 3, you are granted additional
+ permissions described in the GCC Runtime Library Exception, version
+ 3.1, as published by the Free Software Foundation.
+
+ You should have received a copy of the GNU General Public License and
+ a copy of the GCC Runtime Library Exception along with this program;
+ see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
+ <http://www.gnu.org/licenses/>. */
+
+#ifndef _IMMINTRIN_H_INCLUDED
+#error "Never use <avx512vbmi2intrin.h> directly; include <immintrin.h> instead."
+#endif
+
+#ifndef __AVX512VBMI2INTRIN_H_INCLUDED
+#define __AVX512VBMI2INTRIN_H_INCLUDED
+
+#if !defined(__AVX512VBMI2__) || !defined(__AVX512BW__)
+#pragma GCC push_options
+#pragma GCC target("avx512vbmi2,avx512bw")
+#define __DISABLE_AVX512VBMI2BW__
+#endif /* __AVX512VBMI2BW__ */
+
+extern __inline __m512i
+__attribute__((__gnu_inline__, __always_inline__, __artificial__))
+_mm512_mask_compress_epi8 (__m512i __A, __mmask64 __B, __m512i __C)
+{
+ return (__m512i) __builtin_ia32_compressqi512_mask ((__v64qi)__C,
+ (__v64qi)__A, (__mmask64)__B);
+}
+
+
+extern __inline __m512i
+__attribute__((__gnu_inline__, __always_inline__, __artificial__))
+_mm512_maskz_compress_epi8 (__mmask64 __A, __m512i __B)
+{
+ return (__m512i) __builtin_ia32_compressqi512_mask ((__v64qi)__B,
+ (__v64qi)_mm512_setzero_si512 (), (__mmask64)__A);
+}
+
+
+extern __inline void
+__attribute__((__gnu_inline__, __always_inline__, __artificial__))
+_mm512_mask_compressstoreu_epi8 (void * __A, __mmask64 __B, __m512i __C)
+{
+ __builtin_ia32_compressstoreuqi512_mask ((__v64qi *) __A, (__v64qi) __C,
+ (__mmask64) __B);
+}
+
+extern __inline __m512i
+__attribute__((__gnu_inline__, __always_inline__, __artificial__))
+_mm512_mask_compress_epi16 (__m512i __A, __mmask32 __B, __m512i __C)
+{
+ return (__m512i) __builtin_ia32_compresshi512_mask ((__v32hi)__C,
+ (__v32hi)__A, (__mmask32)__B);
+}
+
+extern __inline __m512i
+__attribute__((__gnu_inline__, __always_inline__, __artificial__))
+_mm512_maskz_compress_epi16 (__mmask32 __A, __m512i __B)
+{
+ return (__m512i) __builtin_ia32_compresshi512_mask ((__v32hi)__B,
+ (__v32hi)_mm512_setzero_si512 (), (__mmask32)__A);
+}
+
+extern __inline void
+__attribute__((__gnu_inline__, __always_inline__, __artificial__))
+_mm512_mask_compressstoreu_epi16 (void * __A, __mmask32 __B, __m512i __C)
+{
+ __builtin_ia32_compressstoreuhi512_mask ((__v32hi *) __A, (__v32hi) __C,
+ (__mmask32) __B);
+}
+#ifdef __DISABLE_AVX512VBMI2BW__
+#undef __DISABLE_AVX512VBMI2BW__
+
+#pragma GCC pop_options
+#endif /* __DISABLE_AVX512VBMI2BW__ */
+
+#endif /* __AVX512VBMI2INTRIN_H_INCLUDED */
--- /dev/null
+/* Copyright (C) 2013-2017 Free Software Foundation, Inc.
+
+ This file is part of GCC.
+
+ GCC is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3, or (at your option)
+ any later version.
+
+ GCC is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ Under Section 7 of GPL version 3, you are granted additional
+ permissions described in the GCC Runtime Library Exception, version
+ 3.1, as published by the Free Software Foundation.
+
+ You should have received a copy of the GNU General Public License and
+ a copy of the GCC Runtime Library Exception along with this program;
+ see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
+ <http://www.gnu.org/licenses/>. */
+
+#ifndef _IMMINTRIN_H_INCLUDED
+#error "Never use <avx512vbmi2vlintrin.h> directly; include <immintrin.h> instead."
+#endif
+
+#ifndef _AVX512VBMI2VLINTRIN_H_INCLUDED
+#define _AVX512VBMI2VLINTRIN_H_INCLUDED
+
+#if !defined(__AVX512VL__) || !defined(__AVX512VBMI2__)
+#pragma GCC push_options
+#pragma GCC target("avx512vbmi2,avx512vl")
+#define __DISABLE_AVX512VBMI2VL__
+#endif /* __AVX512VBMIVL__ */
+
+extern __inline __m128i
+__attribute__((__gnu_inline__, __always_inline__, __artificial__))
+_mm_mask_compress_epi8 (__m128i __A, __mmask16 __B, __m128i __C)
+{
+ return (__m128i) __builtin_ia32_compressqi128_mask ((__v16qi)__C,
+ (__v16qi)__A, (__mmask16)__B);
+}
+
+extern __inline __m128i
+__attribute__((__gnu_inline__, __always_inline__, __artificial__))
+_mm_maskz_compress_epi8 (__mmask16 __A, __m128i __B)
+{
+ return (__m128i) __builtin_ia32_compressqi128_mask ((__v16qi) __B,
+ (__v16qi) _mm_setzero_si128 (), (__mmask16) __A);
+}
+
+
+extern __inline void
+__attribute__((__gnu_inline__, __always_inline__, __artificial__))
+_mm256_mask_compressstoreu_epi16 (void * __A, __mmask16 __B, __m256i __C)
+{
+ __builtin_ia32_compressstoreuhi256_mask ((__v16hi *) __A, (__v16hi) __C,
+ (__mmask16) __B);
+}
+
+extern __inline __m128i
+__attribute__((__gnu_inline__, __always_inline__, __artificial__))
+_mm_mask_compress_epi16 (__m128i __A, __mmask8 __B, __m128i __C)
+{
+ return (__m128i) __builtin_ia32_compresshi128_mask ((__v8hi)__C, (__v8hi)__A,
+ (__mmask8)__B);
+}
+
+extern __inline __m128i
+__attribute__((__gnu_inline__, __always_inline__, __artificial__))
+_mm_maskz_compress_epi16 (__mmask8 __A, __m128i __B)
+{
+ return (__m128i) __builtin_ia32_compresshi128_mask ((__v8hi) __B,
+ (__v8hi) _mm_setzero_si128 (), (__mmask8) __A);
+}
+
+extern __inline __m256i
+__attribute__((__gnu_inline__, __always_inline__, __artificial__))
+_mm256_mask_compress_epi16 (__m256i __A, __mmask16 __B, __m256i __C)
+{
+ return (__m256i) __builtin_ia32_compresshi256_mask ((__v16hi)__C,
+ (__v16hi)__A, (__mmask16)__B);
+}
+
+extern __inline __m256i
+__attribute__((__gnu_inline__, __always_inline__, __artificial__))
+_mm256_maskz_compress_epi16 (__mmask16 __A, __m256i __B)
+{
+ return (__m256i) __builtin_ia32_compresshi256_mask ((__v16hi) __B,
+ (__v16hi) _mm256_setzero_si256 (), (__mmask16) __A);
+}
+
+extern __inline void
+__attribute__((__gnu_inline__, __always_inline__, __artificial__))
+_mm_mask_compressstoreu_epi8 (void * __A, __mmask16 __B, __m128i __C)
+{
+ __builtin_ia32_compressstoreuqi128_mask ((__v16qi *) __A, (__v16qi) __C,
+ (__mmask16) __B);
+}
+
+extern __inline void
+__attribute__((__gnu_inline__, __always_inline__, __artificial__))
+_mm_mask_compressstoreu_epi16 (void * __A, __mmask8 __B, __m128i __C)
+{
+ __builtin_ia32_compressstoreuhi128_mask ((__v8hi *) __A, (__v8hi) __C,
+ (__mmask8) __B);
+}
+#ifdef __DISABLE_AVX512VBMI2VL__
+#undef __DISABLE_AVX512VBMI2VL__
+#pragma GCC pop_options
+#endif /* __DISABLE_AVX512VBMIVL__ */
+
+#if !defined(__AVX512VL__) || !defined(__AVX512VBMI2__) || \
+ !defined(__AVX512BW__)
+#pragma GCC push_options
+#pragma GCC target("avx512vbmi2,avx512vl,avx512bw")
+#define __DISABLE_AVX512VBMI2VLBW__
+#endif /* __AVX512VBMIVLBW__ */
+
+extern __inline __m256i
+__attribute__((__gnu_inline__, __always_inline__, __artificial__))
+_mm256_mask_compress_epi8 (__m256i __A, __mmask32 __B, __m256i __C)
+{
+ return (__m256i) __builtin_ia32_compressqi256_mask ((__v32qi)__C,
+ (__v32qi)__A, (__mmask32)__B);
+}
+
+extern __inline __m256i
+__attribute__((__gnu_inline__, __always_inline__, __artificial__))
+_mm256_maskz_compress_epi8 (__mmask32 __A, __m256i __B)
+{
+ return (__m256i) __builtin_ia32_compressqi256_mask ((__v32qi) __B,
+ (__v32qi) _mm256_setzero_si256 (), (__mmask32) __A);
+}
+
+extern __inline void
+__attribute__((__gnu_inline__, __always_inline__, __artificial__))
+_mm256_mask_compressstoreu_epi8 (void * __A, __mmask32 __B, __m256i __C)
+{
+ __builtin_ia32_compressstoreuqi256_mask ((__v32qi *) __A, (__v32qi) __C,
+ (__mmask32) __B);
+}
+
+#ifdef __DISABLE_AVX512VBMI2VLBW__
+#undef __DISABLE_AVX512VBMI2VLBW__
+#pragma GCC pop_options
+#endif /* __DISABLE_AVX512VBMIVLBW__ */
+
+#endif /* _AVX512VBMIVLINTRIN_H_INCLUDED */
IX86_BUILTIN__BDESC_ARGS_LAST, 1);
BDESC_VERIFYS (IX86_BUILTIN__BDESC_ARGS2_FIRST,
IX86_BUILTIN__BDESC_ROUND_ARGS_LAST, 1);
-BDESC_VERIFYS (IX86_BUILTIN__BDESC_MPX_FIRST,
+BDESC_VERIFYS (IX86_BUILTIN__BDESC_SPECIAL_ARGS2_FIRST,
IX86_BUILTIN__BDESC_ARGS2_LAST, 1);
+BDESC_VERIFYS (IX86_BUILTIN__BDESC_MPX_FIRST,
+ IX86_BUILTIN__BDESC_SPECIAL_ARGS2_LAST, 1);
BDESC_VERIFYS (IX86_BUILTIN__BDESC_MPX_CONST_FIRST,
IX86_BUILTIN__BDESC_MPX_LAST, 1);
BDESC_VERIFYS (IX86_BUILTIN__BDESC_MULTI_ARG_FIRST,
i < ARRAY_SIZE (bdesc_args2);
i++, d++)
{
+ BDESC_VERIFY (d->code, IX86_BUILTIN__BDESC_ARGS2_FIRST, i);
if (d->name == 0)
continue;
ftype = (enum ix86_builtin_func_type) d->flag;
def_builtin_const2 (d->mask, d->name, ftype, d->code);
}
+ BDESC_VERIFYS (IX86_BUILTIN__BDESC_ARGS2_LAST,
+ IX86_BUILTIN__BDESC_ARGS2_FIRST,
+ ARRAY_SIZE (bdesc_args2) - 1);
+
+ for (i = 0, d = bdesc_special_args2;
+ i < ARRAY_SIZE (bdesc_special_args2);
+ i++, d++)
+ {
+ BDESC_VERIFY (d->code, IX86_BUILTIN__BDESC_SPECIAL_ARGS2_FIRST, i);
+ if (d->name == 0)
+ continue;
+
+ ftype = (enum ix86_builtin_func_type) d->flag;
+ def_builtin2 (d->mask, d->name, ftype, d->code);
+ }
+ BDESC_VERIFYS (IX86_BUILTIN__BDESC_SPECIAL_ARGS2_LAST,
+ IX86_BUILTIN__BDESC_SPECIAL_ARGS2_FIRST,
+ ARRAY_SIZE (bdesc_special_args2) - 1);
/* Add all builtins with rounding. */
for (i = 0, d = bdesc_round_args;
case VOID_FTYPE_PV16SI_V16SI_UHI:
case VOID_FTYPE_PV8SI_V8SI_UQI:
case VOID_FTYPE_PV4SI_V4SI_UQI:
+ case VOID_FTYPE_PV64QI_V64QI_UDI:
+ case VOID_FTYPE_PV32HI_V32HI_USI:
+ case VOID_FTYPE_PV32QI_V32QI_USI:
+ case VOID_FTYPE_PV16QI_V16QI_UHI:
+ case VOID_FTYPE_PV16HI_V16HI_UHI:
+ case VOID_FTYPE_PV8HI_V8HI_UQI:
switch (icode)
{
/* These builtins and instructions require the memory
}
}
+ if (fcode >= IX86_BUILTIN__BDESC_SPECIAL_ARGS2_FIRST
+ && fcode <= IX86_BUILTIN__BDESC_SPECIAL_ARGS2_LAST)
+ {
+ i = fcode - IX86_BUILTIN__BDESC_SPECIAL_ARGS2_FIRST;
+ return ix86_expand_special_args_builtin (bdesc_special_args2 + i, exp,
+ target);
+ }
+
if (fcode >= IX86_BUILTIN__BDESC_COMI_FIRST
&& fcode <= IX86_BUILTIN__BDESC_COMI_LAST)
{
#include <avx512vpopcntdqintrin.h>
+#include <avx512vbmi2intrin.h>
+
+#include <avx512vbmi2vlintrin.h>
+
#include <shaintrin.h>
#include <lzcntintrin.h>
[V64QI (V16QI "TARGET_AVX512VL") (V32QI "TARGET_AVX512VL")
V32HI (V16HI "TARGET_AVX512VL") (V8HI "TARGET_AVX512VL")])
+;; Same iterator, but without supposed TARGET_AVX512BW
+(define_mode_iterator VI12_AVX512VLBW
+ [(V64QI "TARGET_AVX512BW") (V16QI "TARGET_AVX512VL")
+ (V32QI "TARGET_AVX512VL && TARGET_AVX512BW") (V32HI "TARGET_AVX512BW")
+ (V16HI "TARGET_AVX512VL") (V8HI "TARGET_AVX512VL")])
+
(define_mode_iterator VI1_AVX512VL
[V64QI (V16QI "TARGET_AVX512VL") (V32QI "TARGET_AVX512VL")])
(set_attr "prefix" "evex")
(set_attr "mode" "<sseinsnmode>")])
+(define_insn "compress<mode>_mask"
+ [(set (match_operand:VI12_AVX512VLBW 0 "register_operand" "=v")
+ (unspec:VI12_AVX512VLBW
+ [(match_operand:VI12_AVX512VLBW 1 "register_operand" "v")
+ (match_operand:VI12_AVX512VLBW 2 "vector_move_operand" "0C")
+ (match_operand:<avx512fmaskmode> 3 "register_operand" "Yk")]
+ UNSPEC_COMPRESS))]
+ "TARGET_AVX512VBMI2"
+ "vpcompress<ssemodesuffix>\t{%1, %0%{%3%}%N2|%0%{%3%}%N2, %1}"
+ [(set_attr "type" "ssemov")
+ (set_attr "prefix" "evex")
+ (set_attr "mode" "<sseinsnmode>")])
+
(define_insn "<avx512>_compressstore<mode>_mask"
[(set (match_operand:VI48F 0 "memory_operand" "=m")
(unspec:VI48F
(set_attr "memory" "store")
(set_attr "mode" "<sseinsnmode>")])
+(define_insn "compressstore<mode>_mask"
+ [(set (match_operand:VI12_AVX512VLBW 0 "memory_operand" "=m")
+ (unspec:VI12_AVX512VLBW
+ [(match_operand:VI12_AVX512VLBW 1 "register_operand" "x")
+ (match_dup 0)
+ (match_operand:<avx512fmaskmode> 2 "register_operand" "Yk")]
+ UNSPEC_COMPRESS_STORE))]
+ "TARGET_AVX512VBMI2"
+ "vpcompress<ssemodesuffix>\t{%1, %0%{%2%}|%0%{%2%}, %1}"
+ [(set_attr "type" "ssemov")
+ (set_attr "prefix" "evex")
+ (set_attr "memory" "store")
+ (set_attr "mode" "<sseinsnmode>")])
+
(define_expand "<avx512>_expand<mode>_maskz"
[(set (match_operand:VI48F 0 "register_operand")
(unspec:VI48F
+2017-11-16 Julia Koval <julia.koval@intel.com>
+
+ gcc.target/i386/avx512-check.h: Handle AVX512VBMI2 bit.
+ gcc.target/i386/avx512f-vpcompressb-1.c: New test.
+ gcc.target/i386/avx512f-vpcompressb-2.c: Ditto.
+ gcc.target/i386/avx512f-vpcompressw-1.c: Ditto.
+ gcc.target/i386/avx512f-vpcompressw-2.c: Ditto.
+ gcc.target/i386/avx512vl-vpcompressb-1.c: Ditto.
+ gcc.target/i386/avx512vl-vpcompressb-2.c: Ditto.
+ gcc.target/i386/avx512vl-vpcompressw-1.c: Ditto.
+ gcc.target/i386/avx512vl-vpcompressw-2.c: Ditto.
+ gcc.target/i386/i386.exp (check_effective_target_avx512vbmi2): New.
+
2017-11-23 Jakub Jelinek <jakub@redhat.com>
* gcc.dg/gomp/declare-simd-1.c (f9): Remove.
#endif
#ifdef GFNI
&& (ecx & bit_GFNI)
+#endif
+#ifdef AVX512VBMI2
+ && (ecx & bit_AVX512VBMI2)
#endif
&& avx512f_os_support ())
{
--- /dev/null
+/* { dg-do compile } */
+/* { dg-options "-mavx512f -mavx512vbmi2 -mavx512bw -O2" } */
+/* { dg-final { scan-assembler-times "vpcompressb\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vpcompressb\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\{%k\[1-7\]\}\{z\}(?:\n|\[ \\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vpcompressb\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\n\]*\\)\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 1 } } */
+
+#include <immintrin.h>
+
+int *p;
+volatile __m512i x;
+volatile __mmask64 m;
+
+void extern
+avx512f_test (void)
+{
+ x = _mm512_mask_compress_epi8 (x, m, x);
+ x = _mm512_maskz_compress_epi8 (m, x);
+
+ _mm512_mask_compressstoreu_epi8 (p, m, x);
+}
--- /dev/null
+/* { dg-do run } */
+/* { dg-options "-O2 -mavx512f -mavx512bw -mavx512vbmi2" } */
+/* { dg-require-effective-target avx512f } */
+/* { dg-require-effective-target avx512vbmi2 } */
+
+#define AVX512F
+
+#define AVX512VBMI2
+#include "avx512f-helper.h"
+
+#define SIZE (AVX512F_LEN / 8)
+#include "avx512f-mask-type.h"
+#include <x86intrin.h>
+
+static void
+CALC (char *s, char *r, MASK_TYPE mask)
+{
+ int i, k;
+
+ for (i = 0, k = 0; i < SIZE; i++)
+ {
+ if (mask & ((long long)1 << i))
+ r[k++] = s[i];
+ }
+}
+
+void
+TEST (void)
+{
+ UNION_TYPE (AVX512F_LEN, i_b) s, res1, res2;
+ char res3[SIZE];
+ MASK_TYPE compressed_mask, mask = MASK_VALUE;
+ char res_ref[SIZE];
+ long long i, mask_bit_count, sign = 1;
+
+ for (i = 0; i < SIZE; i++)
+ {
+ s.a[i] = 12345 * (i + 200) * sign;
+ res1.a[i] = DEFAULT_VALUE;
+ res3[i] = DEFAULT_VALUE;
+ sign = -sign;
+ }
+
+ res1.x = INTRINSIC (_mask_compress_epi8) (res1.x, mask, s.x);
+ res2.x = INTRINSIC (_maskz_compress_epi8) (mask, s.x);
+ INTRINSIC (_mask_compressstoreu_epi8) (res3, mask, s.x);
+
+ // Swt
+ if (AVX512F_LEN == 512)
+ mask_bit_count = __popcntq(mask);
+ else
+ mask_bit_count = __popcntd(mask);
+ compressed_mask = ((long long)1 << mask_bit_count) - 1;
+ CALC (s.a, res_ref, mask);
+
+ MASK_MERGE (i_b) (res_ref, compressed_mask, SIZE);
+ if (UNION_CHECK (AVX512F_LEN, i_b) (res1, res_ref))
+ abort ();
+
+ MASK_ZERO (i_b) (res_ref, compressed_mask, SIZE);
+ if (UNION_CHECK (AVX512F_LEN, i_b) (res2, res_ref))
+ abort ();
+
+ MASK_MERGE (i_b) (res_ref, compressed_mask, SIZE);
+ if (checkVc (res3, res_ref, SIZE))
+ abort ();
+}
--- /dev/null
+/* { dg-do compile } */
+/* { dg-options "-mavx512f -mavx512vbmi2 -mavx512bw -O2" } */
+/* { dg-final { scan-assembler-times "vpcompressw\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vpcompressw\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\{%k\[1-7\]\}\{z\}(?:\n|\[ \\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vpcompressw\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\n\]*\\)\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 1 } } */
+
+#include <immintrin.h>
+
+int *p;
+volatile __m512i x;
+volatile __mmask32 m;
+
+void extern
+avx512f_test (void)
+{
+ x = _mm512_mask_compress_epi16 (x, m, x);
+ x = _mm512_maskz_compress_epi16 (m, x);
+
+ _mm512_mask_compressstoreu_epi16 (p, m, x);
+}
--- /dev/null
+/* { dg-do run } */
+/* { dg-options "-O2 -mavx512f -mavx512bw -mavx512vbmi2" } */
+/* { dg-require-effective-target avx512f } */
+/* { dg-require-effective-target avx512vbmi2 } */
+
+#define AVX512F
+
+#define AVX512VBMI2
+#include "avx512f-helper.h"
+
+#define SIZE (AVX512F_LEN / 16)
+#include "avx512f-mask-type.h"
+#include <x86intrin.h>
+
+static void
+CALC (short *s, short *r, MASK_TYPE mask)
+{
+ int i, k;
+
+ for (i = 0, k = 0; i < SIZE; i++)
+ {
+ if (mask & ((long long)1 << i))
+ r[k++] = s[i];
+ }
+}
+
+void
+TEST (void)
+{
+ UNION_TYPE (AVX512F_LEN, i_w) s, res1, res2;
+ short res3[SIZE];
+ MASK_TYPE compressed_mask, mask = MASK_VALUE;
+ short res_ref[SIZE];
+ int i, mask_bit_count, sign = 1;
+
+ for (i = 0; i < SIZE; i++)
+ {
+ s.a[i] = 12345 * (i + 200) * sign;
+ res1.a[i] = DEFAULT_VALUE;
+ res3[i] = DEFAULT_VALUE;
+ sign = -sign;
+ }
+
+ res1.x = INTRINSIC (_mask_compress_epi16) (res1.x, mask, s.x);
+ res2.x = INTRINSIC (_maskz_compress_epi16) (mask, s.x);
+ INTRINSIC (_mask_compressstoreu_epi16) (res3, mask, s.x);
+
+ mask_bit_count = __popcntd (mask);
+ compressed_mask = ((long long)1 << mask_bit_count) - 1;
+ CALC (s.a, res_ref, mask);
+
+ MASK_MERGE (i_w) (res_ref, compressed_mask, SIZE);
+
+ if (UNION_CHECK (AVX512F_LEN, i_w) (res1, res_ref))
+ abort ();
+
+ MASK_ZERO (i_w) (res_ref, compressed_mask, SIZE);
+ if (UNION_CHECK (AVX512F_LEN, i_w) (res2, res_ref))
+ abort ();
+
+ MASK_MERGE (i_w) (res_ref, compressed_mask, SIZE);
+ if (checkVs (res3, res_ref, SIZE))
+ abort ();
+}
--- /dev/null
+/* { dg-do compile } */
+/* { dg-options "-mavx512vl -mavx512vbmi2 -mavx512bw -O2" } */
+/* { dg-final { scan-assembler-times "vpcompressb\[ \\t\]+\[^\{\n\]*%ymm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vpcompressb\[ \\t\]+\[^\{\n\]*%xmm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vpcompressb\[ \\t\]+\[^\{\n\]*%ymm\[0-9\]+\{%k\[1-7\]\}\{z\}(?:\n|\[ \\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vpcompressb\[ \\t\]+\[^\{\n\]*%xmm\[0-9\]+\{%k\[1-7\]\}\{z\}(?:\n|\[ \\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vpcompressb\[ \\t\]+\[^\{\n\]*%ymm\[0-9\]+\[^\n\]*\\)\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vpcompressb\[ \\t\]+\[^\{\n\]*%xmm\[0-9\]+\[^\n\]*\\)\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 1 } } */
+
+#include <immintrin.h>
+
+int *p;
+volatile __m256i x1;
+volatile __m128i x2;
+volatile __mmask16 m16;
+volatile __mmask32 m32;
+
+void extern
+avx512vl_test (void)
+{
+ x1 = _mm256_mask_compress_epi8 (x1, m32, x1);
+ x2 = _mm_mask_compress_epi8 (x2, m16, x2);
+
+ x1 = _mm256_maskz_compress_epi8 (m32, x1);
+ x2 = _mm_maskz_compress_epi8 (m16, x2);
+
+ _mm256_mask_compressstoreu_epi8 (p, m32, x1);
+ _mm_mask_compressstoreu_epi8 (p, m16, x2);
+}
--- /dev/null
+/* { dg-do run } */
+/* { dg-options "-O2 -mavx512vl -mavx512bw -mavx512vbmi2" } */
+/* { dg-require-effective-target avx512vl } */
+/* { dg-require-effective-target avx512vbmi2 } */
+
+#define AVX512VL
+#define AVX512F_LEN 256
+#define AVX512F_LEN_HALF 128
+#include "avx512f-vpcompressb-2.c"
+
+#undef AVX512F_LEN
+#undef AVX512F_LEN_HALF
+
+#define AVX512F_LEN 128
+#define AVX512F_LEN_HALF 128
+#include "avx512f-vpcompressb-2.c"
--- /dev/null
+/* { dg-do compile } */
+/* { dg-options "-mavx512vl -mavx512vbmi2 -O2" } */
+/* { dg-final { scan-assembler-times "vpcompressw\[ \\t\]+\[^\{\n\]*%ymm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vpcompressw\[ \\t\]+\[^\{\n\]*%xmm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vpcompressw\[ \\t\]+\[^\{\n\]*%ymm\[0-9\]+\{%k\[1-7\]\}\{z\}(?:\n|\[ \\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vpcompressw\[ \\t\]+\[^\{\n\]*%xmm\[0-9\]+\{%k\[1-7\]\}\{z\}(?:\n|\[ \\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vpcompressw\[ \\t\]+\[^\{\n\]*%ymm\[0-9\]+\[^\n\]*\\)\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vpcompressw\[ \\t\]+\[^\{\n\]*%xmm\[0-9\]+\[^\n\]*\\)\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 1 } } */
+
+#include <immintrin.h>
+
+int *p;
+volatile __m256i x1;
+volatile __m128i x2;
+volatile __mmask8 m8;
+volatile __mmask16 m16;
+
+void extern
+avx512vl_test (void)
+{
+ x1 = _mm256_mask_compress_epi16 (x1, m16, x1);
+ x2 = _mm_mask_compress_epi16 (x2, m8, x2);
+
+ x1 = _mm256_maskz_compress_epi16 (m16, x1);
+ x2 = _mm_maskz_compress_epi16 (m8, x2);
+
+ _mm256_mask_compressstoreu_epi16 (p, m16, x1);
+ _mm_mask_compressstoreu_epi16 (p, m8, x2);
+}
--- /dev/null
+/* { dg-do run } */
+/* { dg-options "-O2 -mavx512vl -mavx512bw -mavx512vbmi2" } */
+/* { dg-require-effective-target avx512vl } */
+/* { dg-require-effective-target avx512vbmi2 } */
+
+#define AVX512VL
+#define AVX512F_LEN 256
+#define AVX512F_LEN_HALF 128
+#include "avx512f-vpcompressw-2.c"
+
+#undef AVX512F_LEN
+#undef AVX512F_LEN_HALF
+
+#define AVX512F_LEN 128
+#define AVX512F_LEN_HALF 128
+#include "avx512f-vpcompressw-2.c"
} "-mgfni" ]
}
+# Return 1 if avx512vbmi2 instructions can be compiled.
+proc check_effective_target_avx512vbmi2 { } {
+ return [check_no_compiler_messages avx512vbmi2 object {
+ typedef char __v16qi __attribute__ ((__vector_size__ (16)));
+ typedef unsigned long long __mmask16;
+
+ __v16qi
+ _mm_mask_compress_epi8 (__v16qi __A, __mmask16 __B, __v16qi __C)
+ {
+ return (__v16qi) __builtin_ia32_compressqi128_mask((__v16qi)__C,
+ (__v16qi)__A,
+ (__mmask16)__B);
+ }
+ } "-mavx512vbmi2 -mavx512vl" ]
+}
+
+
# If a testcase doesn't have special options, use these.
global DEFAULT_CFLAGS
if ![info exists DEFAULT_CFLAGS] then {
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