Avoid timing violation on ECP5 PHY PAUSE signal

diff --git a/examples/headless/main.c b/examples/headless/main.c
index 37d22bdb9ee8f36623bee50c206d90c51b31a9d1..43bfab7830518df97fd067e97768646dd7c19772 100644 (file)
--- a/examples/headless/main.c
+++ b/examples/headless/main.c
@@ -131,10 +131,10 @@ int main(int argc, char *argv[]) {
 #if 1
        struct gramProfile profile = {
                .mode_registers = {
-                       0xb20, 0x806, 0x200, 0x0
+                       0xb30, 0x806, 0x200, 0x0
                },
-               .rdly_p0 = 2,
-               .rdly_p1 = 2,
+               .rdly_p0 = 5,
+               .rdly_p1 = 5,
        };
 #endif
 #if 0
@@ -167,7 +167,7 @@ int main(int argc, char *argv[]) {
        gram_init(&ctx, &profile, (void*)ddr_base, (void*)0x00009000, (void*)0x00008000);
        printf("done\n");
 
-#if 0
+#if 1
        printf("Rdly\np0: ");
        for (size_t i = 0; i < 8; i++) {
                profile2.rdly_p0 = i;
@@ -201,7 +201,9 @@ int main(int argc, char *argv[]) {
                fflush(stdout);
        }
        printf("\n");
+#endif
 
+#if 0
         printf("Auto calibrating... ");
         res = gram_generate_calibration(&ctx, &profile2);
         if (res != GRAM_ERR_NONE) {

diff --git a/gram/phy/ecp5ddrphy.py b/gram/phy/ecp5ddrphy.py
index 32a679244b4dd639001f4805503b82993d2fb03d..007c143cba8c2c7ba3209246e549ad08d44ade77 100644 (file)
--- a/gram/phy/ecp5ddrphy.py
+++ b/gram/phy/ecp5ddrphy.py
@@ -101,10 +101,28 @@ class _DQSBUFMSettingManager(Elaboratable):
             with m.State("Idle"):
                 with m.If(self.rdly_csr.w_stb):
                     m.d.sync += self.pause.eq(1)
-                    m.next = "RdlyUpdateRequested"
+                    m.next = "RdlyUpdateRequestedDelay1"
+
+            with m.State("RdlyUpdateRequestedDelay1"):
+                m.next = "RdlyUpdateRequestedDelay2"
+
+            with m.State("RdlyUpdateRequestedDelay2"):
+                m.next = "RdlyUpdateRequestedDelay3"
+
+            with m.State("RdlyUpdateRequestedDelay3"):
+                m.next = "RdlyUpdateRequested"
 
             with m.State("RdlyUpdateRequested"):
                 m.d.sync += self.readclksel.eq(self.rdly_csr.w_data)
+                m.next = "ResetPauseDelay1"
+
+            with m.State("ResetPauseDelay1"):
+                m.next = "ResetPauseDelay2"
+
+            with m.State("ResetPauseDelay2"):
+                m.next = "ResetPauseDelay3"
+
+            with m.State("ResetPauseDelay3"):
                 m.next = "ResetPause"
 
             with m.State("ResetPause"):

diff --git a/libgram/src/dfii.c b/libgram/src/dfii.c
index 17e18dada9b4069698df0d060262fb659423c554..8049a0759b3d303673b2d6a47a73e7ab271dc2ab 100644 (file)
--- a/libgram/src/dfii.c
+++ b/libgram/src/dfii.c
@@ -56,6 +56,12 @@ static void dfii_set_mr(const struct gramCtx *ctx, uint8_t mr, uint16_t val) {
 
 #define MR0_DLL_RESET (1 << 8)
 void dfii_initseq(const struct gramCtx *ctx, const struct gramProfile *profile) {
+       /* Assert reset */
+       dfii_set_p0_address(ctx, 0x0);
+       dfii_set_p0_baddress(ctx, 0);
+       dfii_setcontrol(ctx, 0);
+       cdelay(50000);
+
        /* Release reset */
        dfii_set_p0_address(ctx, 0x0);
        dfii_set_p0_baddress(ctx, 0);