More cleanup

diff --git a/passes/pmgen/xilinx_srl.pmg b/passes/pmgen/xilinx_srl.pmg
index 8bdcb0bcddee4164c88e69544fca23b29bb60af4..45d44247a1abbf192e6ee2f10634651e6e0afddc 100644 (file)
--- a/passes/pmgen/xilinx_srl.pmg
+++ b/passes/pmgen/xilinx_srl.pmg
@@ -13,9 +13,9 @@ endcode
 match first
        select first->type.in($_DFF_N_, $_DFF_P_, $_DFFE_NN_, $_DFFE_NP_, $_DFFE_PN_, $_DFFE_PP_, \FDRE, \FDRE_1)
        select !first->has_keep_attr()
-       select !first->type.in(\FDRE) || !first->hasParam(\IS_R_INVERTED) || !param(first, \IS_R_INVERTED).as_bool()
-       select !first->type.in(\FDRE) || !first->hasParam(\IS_D_INVERTED) || !param(first, \IS_D_INVERTED).as_bool()
-       select !first->type.in(\FDRE, \FDRE_1) || port(first, \R) == State::S0
+       select !first->type.in(\FDRE) || !first->parameters.at(\IS_R_INVERTED, State::S0).as_bool()
+       select !first->type.in(\FDRE) || !first->parameters.at(\IS_D_INVERTED, State::S0).as_bool()
+       select !first->type.in(\FDRE, \FDRE_1) || first->connections_.at(\R, State::S0).is_fully_zero()
        filter !non_first_cells.count(first)
 generate
        SigSpec C = module->addWire(NEW_ID);
@@ -34,8 +34,10 @@ generate
                cell->setPort(\CE, module->addWire(NEW_ID));
                if (r & 1)
                        cell->setPort(\R, module->addWire(NEW_ID));
-               else
-                       cell->setPort(\R, State::S0);
+               else {
+                       if (rng(2) == 0)
+                               cell->setPort(\R, State::S0);
+               }
                break;
        case 2:
        case 3:
@@ -82,9 +84,9 @@ arg en_port
 match first
        select first->type.in($_DFF_N_, $_DFF_P_, $_DFFE_NN_, $_DFFE_NP_, $_DFFE_PN_, $_DFFE_PP_, \FDRE, \FDRE_1)
        select !first->has_keep_attr()
-       select !first->type.in(\FDRE) || !first->hasParam(\IS_R_INVERTED) || !param(first, \IS_R_INVERTED).as_bool()
-       select !first->type.in(\FDRE) || !first->hasParam(\IS_D_INVERTED) || !param(first, \IS_D_INVERTED).as_bool()
-       select !first->type.in(\FDRE, \FDRE_1) || port(first, \R) == State::S0
+       select !first->type.in(\FDRE) || !first->parameters.at(\IS_R_INVERTED, State::S0).as_bool()
+       select !first->type.in(\FDRE) || !first->parameters.at(\IS_D_INVERTED, State::S0).as_bool()
+       select !first->type.in(\FDRE, \FDRE_1) || first->connections_.at(\R, State::S0).is_fully_zero()
 endmatch
 
 code clk_port en_port
@@ -105,7 +107,6 @@ match next
        select !next->has_keep_attr()
        select !port(next, \D)[0].wire->get_bool_attribute(\keep)
        select nusers(port(next, \Q)) == 2
-       select !next->type.in(\FDRE, \FDRE_1) || port(next, \R) == State::S0
        index <IdString> next->type === first->type
        index <SigBit> port(next, \Q) === port(first, \D)
        filter port(next, clk_port) == port(first, clk_port)
@@ -113,7 +114,7 @@ match next
        filter !first->type.in(\FDRE) || next->parameters.at(\IS_C_INVERTED, State::S0).as_bool() == first->parameters.at(\IS_C_INVERTED, State::S0).as_bool()
        filter !first->type.in(\FDRE) || next->parameters.at(\IS_D_INVERTED, State::S0).as_bool() == first->parameters.at(\IS_D_INVERTED, State::S0).as_bool()
        filter !first->type.in(\FDRE) || next->parameters.at(\IS_R_INVERTED, State::S0).as_bool() == first->parameters.at(\IS_R_INVERTED, State::S0).as_bool()
-       filter !first->type.in(\FDRE, \FDRE_1) || port(next, \R) == port(first, \R)
+       filter !first->type.in(\FDRE, \FDRE_1) || next->connections_.at(\R, State::S0).is_fully_zero()
 endmatch
 
 code
@@ -140,14 +141,15 @@ match next
        filter !first->type.in(\FDRE) || next->parameters.at(\IS_C_INVERTED, State::S0).as_bool() == first->parameters.at(\IS_C_INVERTED, State::S0).as_bool()
        filter !first->type.in(\FDRE) || next->parameters.at(\IS_D_INVERTED, State::S0).as_bool() == first->parameters.at(\IS_D_INVERTED, State::S0).as_bool()
        filter !first->type.in(\FDRE) || next->parameters.at(\IS_R_INVERTED, State::S0).as_bool() == first->parameters.at(\IS_R_INVERTED, State::S0).as_bool()
-       filter !first->type.in(\FDRE, \FDRE_1) || port(next, \R) == port(first, \R)
+       filter !first->type.in(\FDRE, \FDRE_1) || next->connections_.at(\R, State::S0).is_fully_zero()
 generate
        Cell *cell = module->addCell(NEW_ID, chain.back()->type);
        cell->setPort(\C, chain.back()->getPort(\C));
        cell->setPort(\D, module->addWire(NEW_ID));
        cell->setPort(\Q, chain.back()->getPort(\D));
        if (cell->type == \FDRE) {
-               cell->setPort(\R, chain.back()->getPort(\R));
+               if (rng(2) == 0)
+                       cell->setPort(\R, chain.back()->connections_.at(\R, State::S0));
                cell->setPort(\CE, chain.back()->getPort(\CE));
        }
        else if (cell->type.begins_with("$_DFFE_"))