Allow reads from tdrdata registers

diff --git a/riscv/processor.cc b/riscv/processor.cc
index 0a7912bd791554454813dd071a978e624c4f1f94..c3c66b7c1c929aeb8d56f8b1f03201eba3235d57 100644 (file)
--- a/riscv/processor.cc
+++ b/riscv/processor.cc
@@ -482,6 +482,9 @@ reg_t processor_t::get_csr(int which)
     case CSR_MEDELEG: return state.medeleg;
     case CSR_MIDELEG: return state.mideleg;
     case CSR_TDRSELECT: return 0;
+    case CSR_TDRDATA1: return 0;
+    case CSR_TDRDATA2: return 0;
+    case CSR_TDRDATA3: return 0;
     case CSR_DCSR:
       {
         uint32_t v = 0;