actorlib/fifo: rewrite

* use classes for less code duplication
* the idea of decorator is to avoid passing common parameters (e.g. clock domain names) in module constructors, so remove those parameters
* style

diff --git a/migen/actorlib/fifo.py b/migen/actorlib/fifo.py
index 3d6f036da825c5dcca2372cd46ee435b227b5c7d..817941c778f73e574433d6ea22d762bc95f0884a 100644 (file)
--- a/migen/actorlib/fifo.py
+++ b/migen/actorlib/fifo.py
@@ -2,40 +2,31 @@ from migen.fhdl.std import *
 from migen.flow.actor import *
 from migen.genlib import fifo
 
-def FIFOWrapper(sink, source, fifo):
-       return [
-                       sink.ack.eq(fifo.writable),
-                       fifo.we.eq(sink.stb & sink.ack),
-                       fifo.din.eq(sink.payload),
-
-                       source.stb.eq(fifo.readable),
-                       source.payload.eq(fifo.dout),
-                       fifo.re.eq(source.ack)
-       ]
-
-class SyncFIFO(Module):
-       def __init__(self, layout, depth):
-
+class _FIFOActor(Module):
+       def __init__(self, fifo_class, layout, depth):
                self.sink = Sink(layout)
                self.source = Source(layout)
                self.busy = Signal()
 
-               _fifo = fifo.SyncFIFO(layout, depth)            
+               ###
 
-               self.submodules += _fifo
+               self.submodules.fifo = fifo_class(layout, depth)
 
-               self.comb += FIFOWrapper(self.sink, self.source, _fifo)
+               self.comb += [
+                       self.sink.ack.eq(self.fifo.writable),
+                       self.fifo.we.eq(self.sink.stb & self.sink.ack),
+                       self.fifo.din.eq(self.sink.payload),
 
-class AsyncFIFO(Module):
-       def __init__(self, layout, depth, cd_write="write", cd_read="read"):
+                       self.source.stb.eq(self.fifo.readable),
+                       self.source.payload.eq(self.fifo.dout),
+                       self.fifo.re.eq(self.source.ack)
+               ]
 
-               self.sink = Sink(layout)
-               self.source = Source(layout)
-               self.busy = Signal()
 
-               _fifo = RenameClockDomains(fifo.AsyncFIFO(layout, depth),
-                       {"write": cd_write, "read": cd_read})
-               self.submodules += _fifo
+class SyncFIFO(_FIFOActor):
+       def __init__(self, layout, depth):
+               _FIFOActor.__init__(self, fifo.SyncFIFO, layout, depth)
 
-               self.comb += FIFOWrapper(self.sink, self.source, _fifo)
-               
\ No newline at end of file
+class AsyncFIFO(_FIFOActor):
+       def __init__(self, layout, depth):
+               _FIFOActor.__init__(self, fifo.AsyncFIFO, layout, depth)