projects
/
nmigen.git
/ commitdiff
commit
grep
author
committer
pickaxe
?
search:
re
summary
|
shortlog
|
log
|
commit
| commitdiff |
tree
raw
|
patch
| inline |
side by side
(parent:
4f5b4a9
)
back.pysim: undriven sync signals should return to previous value.
author
whitequark
<whitequark@whitequark.org>
Fri, 14 Dec 2018 17:25:48 +0000
(17:25 +0000)
committer
whitequark
<whitequark@whitequark.org>
Fri, 14 Dec 2018 17:25:48 +0000
(17:25 +0000)
nmigen/back/pysim.py
patch
|
blob
|
history
diff --git
a/nmigen/back/pysim.py
b/nmigen/back/pysim.py
index ba4f0bcd7d9498c8be1b9cf033de913e7c6f57bc..ca01431ea98ff4d8892a54ceb5a6be012148b9b3 100644
(file)
--- a/
nmigen/back/pysim.py
+++ b/
nmigen/back/pysim.py
@@
-345,6
+345,8
@@
class Simulator:
statements = []
for signal in fragment.iter_comb():
statements.append(signal.eq(signal.reset))
+ for domain, signal in fragment.iter_sync():
+ statements.append(signal.eq(signal))
statements += fragment.statements
def add_funclet(signal, funclet):