Fixed sat handling of $eqx and $nex with unequal port widths

diff --git a/kernel/satgen.h b/kernel/satgen.h
index 67312f440b79062b470c51fdabea101a503b8f0a..05f3310c0ab31748d872a096b6480c8855780f12 100644 (file)
--- a/kernel/satgen.h
+++ b/kernel/satgen.h
@@ -462,6 +462,7 @@ struct SatGen
                        if (model_undef && (cell->type == "$eqx" || cell->type == "$nex")) {
                                std::vector<int> undef_a = importUndefSigSpec(cell->connections.at("\\A"), timestep);
                                std::vector<int> undef_b = importUndefSigSpec(cell->connections.at("\\B"), timestep);
+                               extendSignalWidth(undef_a, undef_b, cell, true);
                                a = ez->vec_or(a, undef_a);
                                b = ez->vec_or(b, undef_b);
                        }
@@ -486,6 +487,7 @@ struct SatGen
                                std::vector<int> undef_a = importUndefSigSpec(cell->connections.at("\\A"), timestep);
                                std::vector<int> undef_b = importUndefSigSpec(cell->connections.at("\\B"), timestep);
                                std::vector<int> undef_y = importUndefSigSpec(cell->connections.at("\\Y"), timestep);
+                               extendSignalWidth(undef_a, undef_b, cell, true);
 
                                if (cell->type == "$eqx")
                                        yy.at(0) = ez->AND(yy.at(0), ez->vec_eq(undef_a, undef_b));