Common memory test now shared

diff --git a/tests/arch/anlogic/memory.v b/tests/arch/anlogic/memory.v
deleted file mode 100644 (file)
index cb7753f..0000000
--- a/tests/arch/anlogic/memory.v
+++ /dev/null
@@ -1,21 +0,0 @@
-module top
-(
-       input [7:0] data_a,
-       input [6:1] addr_a,
-       input we_a, clk,
-       output reg [7:0] q_a
-);
-       // Declare the RAM variable
-       reg [7:0] ram[63:0];
-
-       // Port A
-       always @ (posedge clk)
-       begin
-               if (we_a)
-               begin
-                       ram[addr_a] <= data_a;
-                       q_a <= data_a;
-               end
-               q_a <= ram[addr_a];
-       end
-endmodule

diff --git a/tests/arch/anlogic/memory.ys b/tests/arch/anlogic/memory.ys
index 8c0ce844e9bf5ebe3c52b38a1c742481ae21ed05..87b93c2fe9ec769f1c4606a01bf77dbcc4052a98 100644 (file)
--- a/tests/arch/anlogic/memory.ys
+++ b/tests/arch/anlogic/memory.ys
@@ -1,4 +1,4 @@
-read_verilog memory.v
+read_verilog ../common/memory.v
 hierarchy -top top
 proc
 memory -nomap

diff --git a/tests/arch/common/memory.v b/tests/arch/common/memory.v
new file mode 100644 (file)
index 0000000..cb7753f
--- /dev/null
+++ b/tests/arch/common/memory.v
@@ -0,0 +1,21 @@
+module top
+(
+       input [7:0] data_a,
+       input [6:1] addr_a,
+       input we_a, clk,
+       output reg [7:0] q_a
+);
+       // Declare the RAM variable
+       reg [7:0] ram[63:0];
+
+       // Port A
+       always @ (posedge clk)
+       begin
+               if (we_a)
+               begin
+                       ram[addr_a] <= data_a;
+                       q_a <= data_a;
+               end
+               q_a <= ram[addr_a];
+       end
+endmodule

diff --git a/tests/arch/ecp5/memory.v b/tests/arch/ecp5/memory.v
deleted file mode 100644 (file)
index cb7753f..0000000
--- a/tests/arch/ecp5/memory.v
+++ /dev/null
@@ -1,21 +0,0 @@
-module top
-(
-       input [7:0] data_a,
-       input [6:1] addr_a,
-       input we_a, clk,
-       output reg [7:0] q_a
-);
-       // Declare the RAM variable
-       reg [7:0] ram[63:0];
-
-       // Port A
-       always @ (posedge clk)
-       begin
-               if (we_a)
-               begin
-                       ram[addr_a] <= data_a;
-                       q_a <= data_a;
-               end
-               q_a <= ram[addr_a];
-       end
-endmodule

diff --git a/tests/arch/ecp5/memory.ys b/tests/arch/ecp5/memory.ys
index 9b475f122d8ec6c26944e52d09af5a7d627749a6..c82b7b4054ddc150bf793039d6966476d8e751b4 100644 (file)
--- a/tests/arch/ecp5/memory.ys
+++ b/tests/arch/ecp5/memory.ys
@@ -1,4 +1,4 @@
-read_verilog memory.v
+read_verilog ../common/memory.v
 hierarchy -top top
 proc
 memory -nomap

diff --git a/tests/arch/efinix/memory.v b/tests/arch/efinix/memory.v
deleted file mode 100644 (file)
index 5634d65..0000000
--- a/tests/arch/efinix/memory.v
+++ /dev/null
@@ -1,21 +0,0 @@
-module top
-(
-       input [7:0] data_a,
-       input [8:1] addr_a,
-       input we_a, clk,
-       output reg [7:0] q_a
-);
-       // Declare the RAM variable
-       reg [7:0] ram[63:0];
-
-       // Port A
-       always @ (posedge clk)
-       begin
-               if (we_a)
-               begin
-                       ram[addr_a] <= data_a;
-                       q_a <= data_a;
-               end
-               q_a <= ram[addr_a];
-       end
-endmodule

diff --git a/tests/arch/efinix/memory.ys b/tests/arch/efinix/memory.ys
index fe24b0a9b1c6d5d1ad9b485d62df6cf6f42500a3..6f6acdcde0f699d7a2c55bc809cf654b173b9262 100644 (file)
--- a/tests/arch/efinix/memory.ys
+++ b/tests/arch/efinix/memory.ys
@@ -1,4 +1,4 @@
-read_verilog memory.v
+read_verilog ../common/memory.v
 hierarchy -top top
 proc
 memory -nomap

diff --git a/tests/arch/ice40/memory.v b/tests/arch/ice40/memory.v
deleted file mode 100644 (file)
index cb7753f..0000000
--- a/tests/arch/ice40/memory.v
+++ /dev/null
@@ -1,21 +0,0 @@
-module top
-(
-       input [7:0] data_a,
-       input [6:1] addr_a,
-       input we_a, clk,
-       output reg [7:0] q_a
-);
-       // Declare the RAM variable
-       reg [7:0] ram[63:0];
-
-       // Port A
-       always @ (posedge clk)
-       begin
-               if (we_a)
-               begin
-                       ram[addr_a] <= data_a;
-                       q_a <= data_a;
-               end
-               q_a <= ram[addr_a];
-       end
-endmodule

diff --git a/tests/arch/ice40/memory.ys b/tests/arch/ice40/memory.ys
index a66afbae6f8c7d91b404b3cac326e122c8d097af..c356e67fbb68a0a8acb056d8c63d35d38345ec36 100644 (file)
--- a/tests/arch/ice40/memory.ys
+++ b/tests/arch/ice40/memory.ys
@@ -1,4 +1,4 @@
-read_verilog memory.v
+read_verilog ../common/memory.v
 hierarchy -top top
 proc
 memory -nomap

diff --git a/tests/arch/xilinx/memory.v b/tests/arch/xilinx/memory.v
deleted file mode 100644 (file)
index cb7753f..0000000
--- a/tests/arch/xilinx/memory.v
+++ /dev/null
@@ -1,21 +0,0 @@
-module top
-(
-       input [7:0] data_a,
-       input [6:1] addr_a,
-       input we_a, clk,
-       output reg [7:0] q_a
-);
-       // Declare the RAM variable
-       reg [7:0] ram[63:0];
-
-       // Port A
-       always @ (posedge clk)
-       begin
-               if (we_a)
-               begin
-                       ram[addr_a] <= data_a;
-                       q_a <= data_a;
-               end
-               q_a <= ram[addr_a];
-       end
-endmodule

diff --git a/tests/arch/xilinx/memory.ys b/tests/arch/xilinx/memory.ys
index 5402513a226b0993b4babac239e02c71a011ccd7..da1ed0e49e4cc0ee179312c87f25fcab9c618db7 100644 (file)
--- a/tests/arch/xilinx/memory.ys
+++ b/tests/arch/xilinx/memory.ys
@@ -1,4 +1,4 @@
-read_verilog memory.v
+read_verilog ../common/memory.v
 hierarchy -top top
 proc
 memory -nomap