i965/gen7.5: Fix missing Shader Channel Select entries on Haswell

Probably non-intentional, but the SURFACE_STATE setup refactoring
for buffer surfaces had missed the scs bits when creating constant
surface states.

Fixes broken GLB 2.5 on Haswell where the knight's textures are missing

Signed-off-by: Abdiel Janulgue <abdiel.janulgue@linux.intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

diff --git a/src/mesa/drivers/dri/i965/gen7_wm_surface_state.c b/src/mesa/drivers/dri/i965/gen7_wm_surface_state.c
index 6938b1abc965ab538c55af82accfe38401abebbf..7571cbfadb1b438ab301ae35b303c2eaa4021dfd 100644 (file)
--- a/src/mesa/drivers/dri/i965/gen7_wm_surface_state.c
+++ b/src/mesa/drivers/dri/i965/gen7_wm_surface_state.c
@@ -249,6 +249,13 @@ gen7_emit_buffer_surface_state(struct brw_context *brw,
 
    surf[5] = SET_FIELD(mocs, GEN7_SURFACE_MOCS);
 
+   if (brw->is_haswell) {
+      surf[7] |= (SET_FIELD(HSW_SCS_RED,   GEN7_SURFACE_SCS_R) |
+                  SET_FIELD(HSW_SCS_GREEN, GEN7_SURFACE_SCS_G) |
+                  SET_FIELD(HSW_SCS_BLUE,  GEN7_SURFACE_SCS_B) |
+                  SET_FIELD(HSW_SCS_ALPHA, GEN7_SURFACE_SCS_A));
+   }
+
    /* Emit relocation to surface contents */
    if (bo) {
       drm_intel_bo_emit_reloc(brw->batch.bo, *out_offset + 4,