projects / openpower-isa.git / commitdiff
? search:
summary | shortlog | log | commit | commitdiff | tree
raw | patch | inline | side by side (parent: 2ff083f)
huhn? addpcis converts to .long? huhn?
authorLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Sat, 10 Sep 2022 23:54:49 +0000 (00:54 +0100)
committerLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Sat, 10 Sep 2022 23:54:49 +0000 (00:54 +0100)
src/openpower/sv/trans/test_pysvp64dis.py patch | blob | history

diff --git a/src/openpower/sv/trans/test_pysvp64dis.py b/src/openpower/sv/trans/test_pysvp64dis.py
index daec78c85114ec52cdb0ac12b5e23e9e92c7b8d3..5f9cfc64b14df92b10f2ba9a8bccc3feb799add7 100644 (file)
--- a/src/openpower/sv/trans/test_pysvp64dis.py
+++ b/src/openpower/sv/trans/test_pysvp64dis.py
@@ -40,9 +40,9 @@ class SVSTATETestCase(unittest.TestCase):
 
     def test_2_d_custom_op(self):
         expected = [
-                    'addpcis 12,5',
                     'fishmv 12,2',
                     'fmvis 12,97',
+                    'addpcis 12,5',
                         ]
         self._do_tst(expected)