litescope/bridge: create a generic wishbone bridge that can be used with different...

- we can now pass a phy to LiteScopeWishboneBridge
- LiteScopeUART2Wishbone is only a specific LiteScopeWishboneBridge
- UART mux is removed since complicated and no longer useful (we can now create easily virtual UART over Ethernet, USB or PCIe) or simply add another UART for debug.

diff --git a/misoclib/com/liteeth/example_designs/targets/base.py b/misoclib/com/liteeth/example_designs/targets/base.py
index 83b47ff1ea47f5f2771d058b918646a78a85cd24..5d501df18470bf9ec7b90b75e77925fca8bd99b4 100644 (file)
--- a/misoclib/com/liteeth/example_designs/targets/base.py
+++ b/misoclib/com/liteeth/example_designs/targets/base.py
@@ -4,7 +4,7 @@ from migen.genlib.io import CRG
 
 from misoclib.soc import SoC
 from misoclib.tools.litescope.common import *
-from misoclib.tools.litescope.bridge.uart2wb import LiteScopeUART2WB
+from misoclib.tools.litescope.bridge.wishbone import LiteScopeUART2Wishbone
 from misoclib.tools.litescope.frontend.la import LiteScopeLA
 from misoclib.tools.litescope.core.port import LiteScopeTerm
 
@@ -30,7 +30,7 @@ class BaseSoC(SoC, AutoCSR):
             with_identifier=True,
             with_timer=False
         )
-        self.add_cpu_or_bridge(LiteScopeUART2WB(platform.request("serial"), clk_freq, baudrate=115200))
+        self.add_cpu_or_bridge(LiteScopeUART2Wishbone(platform.request("serial"), clk_freq, baudrate=115200))
         self.add_wb_master(self.cpu_or_bridge.wishbone)
         self.submodules.crg = CRG(platform.request(platform.default_clk_name))
 

diff --git a/misoclib/com/liteeth/example_designs/test/make.py b/misoclib/com/liteeth/example_designs/test/make.py
index aa3c5cceff0531bbf922f8a33df57844692864b8..2922b9a1e846dd8c7df67c45f4323cb06c909974 100755 (executable)
--- a/misoclib/com/liteeth/example_designs/test/make.py
+++ b/misoclib/com/liteeth/example_designs/test/make.py
@@ -19,9 +19,9 @@ def _get_args():
 if __name__ == "__main__":
     args = _get_args()
     if args.bridge == "uart":
-        from misoclib.tools.litescope.host.driver.uart import LiteScopeUARTDriver
+        from misoclib.tools.litescope.host.driver.uart import LiteScopeUART2WishboneDriver
         port = args.port if not args.port.isdigit() else int(args.port)
-        wb = LiteScopeUARTDriver(port, args.baudrate, "./csr.csv", int(args.busword), debug=False)
+        wb = LiteScopeUART2WishboneDriver(port, args.baudrate, "./csr.csv", int(args.busword), debug=False)
     elif args.bridge == "etherbone":
         from misoclib.tools.litescope.host.driver.etherbone import LiteScopeEtherboneDriver
         wb = LiteScopeEtherboneDriver(args.ip_address, int(args.udp_port), "./csr.csv", int(args.busword), debug=False)

diff --git a/misoclib/com/litepcie/example_designs/targets/dma.py b/misoclib/com/litepcie/example_designs/targets/dma.py
index 347836722cc83311ed42e6e4677d02ba279d6a3f..240f5cef262ef629641df18fd5defcff6b80196a 100644 (file)
--- a/misoclib/com/litepcie/example_designs/targets/dma.py
+++ b/misoclib/com/litepcie/example_designs/targets/dma.py
@@ -6,7 +6,7 @@ from migen.genlib.misc import timeline
 
 from misoclib.soc import SoC
 from misoclib.tools.litescope.common import *
-from misoclib.tools.litescope.bridge.uart2wb import LiteScopeUART2WB
+from misoclib.tools.litescope.bridge.wishbone import LiteScopeUART2Wishbone
 
 from misoclib.com.litepcie.phy.s7pciephy import S7PCIEPHY
 from misoclib.com.litepcie.core import Endpoint
@@ -82,7 +82,7 @@ class PCIeDMASoC(SoC, AutoCSR):
         self.dma.source.connect(self.dma.sink)
 
         if with_uart_bridge:
-            self.submodules.uart_bridge = LiteScopeUART2WB(platform.request("serial"), clk_freq, baudrate=115200)
+            self.submodules.uart_bridge = LiteScopeUART2Wishbone(platform.request("serial"), clk_freq, baudrate=115200)
             self.add_wb_master(self.uart_bridge.wishbone)
 
         # IRQs

diff --git a/misoclib/com/litepcie/example_designs/test/make.py b/misoclib/com/litepcie/example_designs/test/make.py
index f29f45a06defe63e392d4461a671b4ad8ef1e50c..c10200004bb0087b1b2e8f9ae69b62202e3b3732 100755 (executable)
--- a/misoclib/com/litepcie/example_designs/test/make.py
+++ b/misoclib/com/litepcie/example_designs/test/make.py
@@ -21,9 +21,9 @@ def _get_args():
 if __name__ == "__main__":
     args = _get_args()
     if args.bridge == "uart":
-        from misoclib.tools.litescope.host.driver.uart import LiteScopeUARTDriver
+        from misoclib.tools.litescope.host.driver.uart import LiteScopeUART2WishboneDriver
         port = args.port if not args.port.isdigit() else int(args.port)
-        wb = LiteScopeUARTDriver(port, args.baudrate, "./csr.csv", int(args.busword), debug=False)
+        wb = LiteScopeUART2WishboneDriver(port, args.baudrate, "./csr.csv", int(args.busword), debug=False)
     elif args.bridge == "etherbone":
         from misoclib.tools.litescope.host.driver.etherbone import LiteScopeEtherboneDriver
         wb = LiteScopeEtherboneDriver(args.ip_address, int(args.udp_port), "./csr.csv", int(args.busword), debug=False)

diff --git a/misoclib/mem/litesata/example_designs/targets/bist.py b/misoclib/mem/litesata/example_designs/targets/bist.py
index e52e85471ab4903c558bdfe91f8dcaa9c99aea5d..3238bd8ffaf019281bcf158dc00e4b9e7f3fb7ee 100644 (file)
--- a/misoclib/mem/litesata/example_designs/targets/bist.py
+++ b/misoclib/mem/litesata/example_designs/targets/bist.py
@@ -6,7 +6,7 @@ from migen.bank.description import *
 from misoclib.soc import SoC
 
 from misoclib.tools.litescope.common import *
-from misoclib.tools.litescope.bridge.uart2wb import LiteScopeUART2WB
+from misoclib.tools.litescope.bridge.wishbone import LiteScopeUART2Wishbone
 from misoclib.tools.litescope.frontend.la import LiteScopeLA
 from misoclib.tools.litescope.core.port import LiteScopeTerm
 
@@ -99,7 +99,7 @@ class BISTSoC(SoC, AutoCSR):
             with_identifier=True,
             with_timer=False
         )
-        self.add_cpu_or_bridge(LiteScopeUART2WB(platform.request("serial"), clk_freq, baudrate=115200))
+        self.add_cpu_or_bridge(LiteScopeUART2Wishbone(platform.request("serial"), clk_freq, baudrate=115200))
         self.add_wb_master(self.cpu_or_bridge.wishbone)
         self.submodules.crg = _CRG(platform)
 

diff --git a/misoclib/mem/litesata/example_designs/test/bist.py b/misoclib/mem/litesata/example_designs/test/bist.py
index 2b27206c991dc2e5d6b3a785d41ec17f61e66567..e610ebf45d182cd0b1c87162daf15509c154ba8e 100644 (file)
--- a/misoclib/mem/litesata/example_designs/test/bist.py
+++ b/misoclib/mem/litesata/example_designs/test/bist.py
@@ -2,7 +2,7 @@ import time
 import argparse
 import random as rand
 from collections import OrderedDict
-from misoclib.tools.litescope.host.driver.uart import LiteScopeUARTDriver
+from misoclib.tools.litescope.host.driver.uart import LiteScopeUART2WishboneDriver
 
 KB = 1024
 MB = 1024*KB
@@ -149,7 +149,7 @@ SATA BIST utility.
 
 if __name__ == "__main__":
     args = _get_args()
-    wb = LiteScopeUARTDriver(args.port, args.baudrate, "./csr.csv", int(args.busword), debug=False)
+    wb = LiteScopeUART2WishboneDriver(args.port, args.baudrate, "./csr.csv", int(args.busword), debug=False)
     wb.open()
     # # #
     identify = LiteSATABISTIdentifyDriver(wb.regs, "sata_bist")

diff --git a/misoclib/mem/litesata/example_designs/test/make.py b/misoclib/mem/litesata/example_designs/test/make.py
index f7a9ec671cc316f27af26bfdb3b6f0e7e2731bf0..472780518f8e0881f369d41d2865caaef047ca86 100755 (executable)
--- a/misoclib/mem/litesata/example_designs/test/make.py
+++ b/misoclib/mem/litesata/example_designs/test/make.py
@@ -19,9 +19,9 @@ def _get_args():
 if __name__ == "__main__":
     args = _get_args()
     if args.bridge == "uart":
-        from misoclib.tools.litescope.host.driver.uart import LiteScopeUARTDriver
+        from misoclib.tools.litescope.host.driver.uart import LiteScopeUART2WishboneDriver
         port = args.port if not args.port.isdigit() else int(args.port)
-        wb = LiteScopeUARTDriver(port, args.baudrate, "./csr.csv", int(args.busword), debug=False)
+        wb = LiteScopeUART2WishboneDriver(port, args.baudrate, "./csr.csv", int(args.busword), debug=False)
     elif args.bridge == "etherbone":
         from misoclib.tools.litescope.host.driver.etherbone import LiteScopeEtherboneDriver
         wb = LiteScopeEtherboneDriver(args.ip_address, int(args.udp_port), "./csr.csv", int(args.busword), debug=False)

diff --git a/misoclib/tools/litescope/bridge/uart2wb.py b/misoclib/tools/litescope/bridge/uart2wb.py
deleted file mode 100644 (file)
index 08e4ec0..0000000
--- a/misoclib/tools/litescope/bridge/uart2wb.py
+++ /dev/null
@@ -1,192 +0,0 @@
-from misoclib.tools.litescope.common import *
-from migen.bus import wishbone
-from migen.genlib.misc import chooser
-from migen.genlib.cdc import MultiReg
-from migen.bank.description import *
-from migen.bank.eventmanager import *
-from migen.genlib.record import Record
-from migen.flow.actor import Sink, Source
-
-from misoclib.com.uart.phy.serial import UARTPHYSerial
-
-
-class UARTPads:
-    def __init__(self):
-        self.rx = Signal()
-        self.tx = Signal()
-
-
-class UARTMux(Module):
-    def __init__(self, pads):
-        self.sel = Signal(max=2)
-        self.shared_pads = UARTPads()
-        self.bridge_pads = UARTPads()
-
-        # # #
-
-        # Route rx pad:
-        # when sel==0, route it to shared rx and bridge rx
-        # when sel==1, route it only to bridge rx
-        self.comb += \
-            If(self.sel == 0,
-                self.shared_pads.rx.eq(pads.rx),
-                self.bridge_pads.rx.eq(pads.rx)
-            ).Else(
-                self.bridge_pads.rx.eq(pads.rx)
-            )
-
-        # Route tx:
-        # when sel==0, route shared tx to pads tx
-        # when sel==1, route bridge tx to pads tx
-        self.comb += \
-            If(self.sel == 0,
-                pads.tx.eq(self.shared_pads.tx)
-            ).Else(
-                pads.tx.eq(self.bridge_pads.tx)
-            )
-
-
-class LiteScopeUART2WB(Module, AutoCSR):
-    cmds = {
-        "write": 0x01,
-        "read": 0x02
-    }
-
-    def __init__(self, pads, clk_freq, baudrate=115200, share_uart=False):
-        self.wishbone = wishbone.Interface()
-        if share_uart:
-            self._sel = CSRStorage()
-
-        # # #
-
-        if share_uart:
-            mux = UARTMux(pads)
-            uart = UARTPHYSerial(mux.bridge_pads, clk_freq, baudrate)
-            self.submodules += mux, uart
-            self.shared_pads = mux.shared_pads
-            self.comb += mux.sel.eq(self._sel.storage)
-        else:
-            uart = UARTPHYSerial(pads, clk_freq, baudrate)
-            self.submodules += uart
-
-        byte_counter = Counter(3)
-        word_counter = Counter(8)
-        self.submodules += byte_counter, word_counter
-
-        cmd = Signal(8)
-        cmd_ce = Signal()
-
-        length = Signal(8)
-        length_ce = Signal()
-
-        address = Signal(32)
-        address_ce = Signal()
-
-        data = Signal(32)
-        rx_data_ce = Signal()
-        tx_data_ce = Signal()
-
-        self.sync += [
-            If(cmd_ce, cmd.eq(uart.source.data)),
-            If(length_ce, length.eq(uart.source.data)),
-            If(address_ce, address.eq(Cat(uart.source.data, address[0:24]))),
-            If(rx_data_ce,
-                data.eq(Cat(uart.source.data, data[0:24]))
-            ).Elif(tx_data_ce,
-                data.eq(self.wishbone.dat_r)
-            )
-        ]
-
-        fsm = InsertReset(FSM(reset_state="IDLE"))
-        timeout = Timeout(clk_freq//10)
-        self.submodules += fsm, timeout
-        self.comb += [
-            timeout.ce.eq(1),
-            fsm.reset.eq(timeout.reached)
-        ]
-        fsm.act("IDLE",
-            timeout.reset.eq(1),
-            If(uart.source.stb,
-                cmd_ce.eq(1),
-                If((uart.source.data == self.cmds["write"]) |
-                   (uart.source.data == self.cmds["read"]),
-                    NextState("RECEIVE_LENGTH")
-                ),
-                byte_counter.reset.eq(1),
-                word_counter.reset.eq(1)
-            )
-        )
-        fsm.act("RECEIVE_LENGTH",
-            If(uart.source.stb,
-                length_ce.eq(1),
-                NextState("RECEIVE_ADDRESS")
-            )
-        )
-        fsm.act("RECEIVE_ADDRESS",
-            If(uart.source.stb,
-                address_ce.eq(1),
-                byte_counter.ce.eq(1),
-                If(byte_counter.value == 3,
-                    If(cmd == self.cmds["write"],
-                        NextState("RECEIVE_DATA")
-                    ).Elif(cmd == self.cmds["read"],
-                        NextState("READ_DATA")
-                    ),
-                    byte_counter.reset.eq(1),
-                )
-            )
-        )
-        fsm.act("RECEIVE_DATA",
-            If(uart.source.stb,
-                rx_data_ce.eq(1),
-                byte_counter.ce.eq(1),
-                If(byte_counter.value == 3,
-                    NextState("WRITE_DATA"),
-                    byte_counter.reset.eq(1)
-                )
-            )
-        )
-        self.comb += [
-            self.wishbone.adr.eq(address + word_counter.value),
-            self.wishbone.dat_w.eq(data),
-            self.wishbone.sel.eq(2**flen(self.wishbone.sel)-1)
-        ]
-        fsm.act("WRITE_DATA",
-            self.wishbone.stb.eq(1),
-            self.wishbone.we.eq(1),
-            self.wishbone.cyc.eq(1),
-            If(self.wishbone.ack,
-                word_counter.ce.eq(1),
-                If(word_counter.value == (length-1),
-                    NextState("IDLE")
-                ).Else(
-                    NextState("RECEIVE_DATA")
-                )
-            )
-        )
-        fsm.act("READ_DATA",
-            self.wishbone.stb.eq(1),
-            self.wishbone.we.eq(0),
-            self.wishbone.cyc.eq(1),
-            If(self.wishbone.ack,
-                tx_data_ce.eq(1),
-                NextState("SEND_DATA")
-            )
-        )
-        self.comb += \
-            chooser(data, byte_counter.value, uart.sink.data, n=4, reverse=True)
-        fsm.act("SEND_DATA",
-            uart.sink.stb.eq(1),
-            If(uart.sink.ack,
-                byte_counter.ce.eq(1),
-                If(byte_counter.value == 3,
-                    word_counter.ce.eq(1),
-                    If(word_counter.value == (length-1),
-                        NextState("IDLE")
-                    ).Else(
-                        NextState("READ_DATA"),
-                        byte_counter.reset.eq(1)
-                    )
-                )
-            )
-        )

diff --git a/misoclib/tools/litescope/bridge/wishbone.py b/misoclib/tools/litescope/bridge/wishbone.py
new file mode 100644 (file)
index 0000000..4930f68
--- /dev/null
+++ b/misoclib/tools/litescope/bridge/wishbone.py
@@ -0,0 +1,145 @@
+from misoclib.tools.litescope.common import *
+from migen.bus import wishbone
+from migen.genlib.misc import chooser
+from migen.genlib.record import Record
+from migen.flow.actor import Sink, Source
+
+from misoclib.com.uart.phy.serial import UARTPHYSerial
+
+class LiteScopeWishboneBridge(Module):
+    cmds = {
+        "write": 0x01,
+        "read": 0x02
+    }
+
+    def __init__(self, phy, clk_freq):
+        self.wishbone = wishbone.Interface()
+
+        # # #
+
+        byte_counter = Counter(3)
+        word_counter = Counter(8)
+        self.submodules += byte_counter, word_counter
+
+        cmd = Signal(8)
+        cmd_ce = Signal()
+
+        length = Signal(8)
+        length_ce = Signal()
+
+        address = Signal(32)
+        address_ce = Signal()
+
+        data = Signal(32)
+        rx_data_ce = Signal()
+        tx_data_ce = Signal()
+
+        self.sync += [
+            If(cmd_ce, cmd.eq(phy.source.data)),
+            If(length_ce, length.eq(phy.source.data)),
+            If(address_ce, address.eq(Cat(phy.source.data, address[0:24]))),
+            If(rx_data_ce,
+                data.eq(Cat(phy.source.data, data[0:24]))
+            ).Elif(tx_data_ce,
+                data.eq(self.wishbone.dat_r)
+            )
+        ]
+
+        fsm = InsertReset(FSM(reset_state="IDLE"))
+        timeout = Timeout(clk_freq//10)
+        self.submodules += fsm, timeout
+        self.comb += [
+            timeout.ce.eq(1),
+            fsm.reset.eq(timeout.reached)
+        ]
+        fsm.act("IDLE",
+            timeout.reset.eq(1),
+            If(phy.source.stb,
+                cmd_ce.eq(1),
+                If((phy.source.data == self.cmds["write"]) |
+                   (phy.source.data == self.cmds["read"]),
+                    NextState("RECEIVE_LENGTH")
+                ),
+                byte_counter.reset.eq(1),
+                word_counter.reset.eq(1)
+            )
+        )
+        fsm.act("RECEIVE_LENGTH",
+            If(phy.source.stb,
+                length_ce.eq(1),
+                NextState("RECEIVE_ADDRESS")
+            )
+        )
+        fsm.act("RECEIVE_ADDRESS",
+            If(phy.source.stb,
+                address_ce.eq(1),
+                byte_counter.ce.eq(1),
+                If(byte_counter.value == 3,
+                    If(cmd == self.cmds["write"],
+                        NextState("RECEIVE_DATA")
+                    ).Elif(cmd == self.cmds["read"],
+                        NextState("READ_DATA")
+                    ),
+                    byte_counter.reset.eq(1),
+                )
+            )
+        )
+        fsm.act("RECEIVE_DATA",
+            If(phy.source.stb,
+                rx_data_ce.eq(1),
+                byte_counter.ce.eq(1),
+                If(byte_counter.value == 3,
+                    NextState("WRITE_DATA"),
+                    byte_counter.reset.eq(1)
+                )
+            )
+        )
+        self.comb += [
+            self.wishbone.adr.eq(address + word_counter.value),
+            self.wishbone.dat_w.eq(data),
+            self.wishbone.sel.eq(2**flen(self.wishbone.sel)-1)
+        ]
+        fsm.act("WRITE_DATA",
+            self.wishbone.stb.eq(1),
+            self.wishbone.we.eq(1),
+            self.wishbone.cyc.eq(1),
+            If(self.wishbone.ack,
+                word_counter.ce.eq(1),
+                If(word_counter.value == (length-1),
+                    NextState("IDLE")
+                ).Else(
+                    NextState("RECEIVE_DATA")
+                )
+            )
+        )
+        fsm.act("READ_DATA",
+            self.wishbone.stb.eq(1),
+            self.wishbone.we.eq(0),
+            self.wishbone.cyc.eq(1),
+            If(self.wishbone.ack,
+                tx_data_ce.eq(1),
+                NextState("SEND_DATA")
+            )
+        )
+        self.comb += \
+            chooser(data, byte_counter.value, phy.sink.data, n=4, reverse=True)
+        fsm.act("SEND_DATA",
+            phy.sink.stb.eq(1),
+            If(phy.sink.ack,
+                byte_counter.ce.eq(1),
+                If(byte_counter.value == 3,
+                    word_counter.ce.eq(1),
+                    If(word_counter.value == (length-1),
+                        NextState("IDLE")
+                    ).Else(
+                        NextState("READ_DATA"),
+                        byte_counter.reset.eq(1)
+                    )
+                )
+            )
+        )
+
+class LiteScopeUART2Wishbone(LiteScopeWishboneBridge):
+    def __init__(self, pads, clk_freq, baudrate=115200):
+        self.submodules.phy = UARTPHYSerial(pads, clk_freq, baudrate)
+        LiteScopeWishboneBridge.__init__(self, self.phy, clk_freq)

diff --git a/misoclib/tools/litescope/example_designs/targets/simple.py b/misoclib/tools/litescope/example_designs/targets/simple.py
index dfc0f3482bd4621fb03bb2ef03bc323b57925ea8..f8ebf7561cd94d29ef9d40a61589cbe8283085fd 100644 (file)
--- a/misoclib/tools/litescope/example_designs/targets/simple.py
+++ b/misoclib/tools/litescope/example_designs/targets/simple.py
@@ -3,7 +3,7 @@ from migen.genlib.io import CRG
 
 from misoclib.soc import SoC
 from misoclib.tools.litescope.common import *
-from misoclib.tools.litescope.bridge.uart2wb import LiteScopeUART2WB
+from misoclib.tools.litescope.bridge.wishbone import LiteScopeUART2Wishbone
 from misoclib.tools.litescope.frontend.io import LiteScopeIO
 from misoclib.tools.litescope.frontend.la import LiteScopeLA
 from misoclib.tools.litescope.core.port import LiteScopeTerm
@@ -25,7 +25,7 @@ class LiteScopeSoC(SoC, AutoCSR):
             with_identifier=True,
             with_timer=False
         )
-        self.add_cpu_or_bridge(LiteScopeUART2WB(platform.request("serial"), clk_freq, baudrate=115200))
+        self.add_cpu_or_bridge(LiteScopeUART2Wishbone(platform.request("serial"), clk_freq, baudrate=115200))
         self.add_wb_master(self.cpu_or_bridge.wishbone)
         self.submodules.crg = CRG(platform.request(platform.default_clk_name))
 

diff --git a/misoclib/tools/litescope/example_designs/test/make.py b/misoclib/tools/litescope/example_designs/test/make.py
index f7a9ec671cc316f27af26bfdb3b6f0e7e2731bf0..472780518f8e0881f369d41d2865caaef047ca86 100755 (executable)
--- a/misoclib/tools/litescope/example_designs/test/make.py
+++ b/misoclib/tools/litescope/example_designs/test/make.py
@@ -19,9 +19,9 @@ def _get_args():
 if __name__ == "__main__":
     args = _get_args()
     if args.bridge == "uart":
-        from misoclib.tools.litescope.host.driver.uart import LiteScopeUARTDriver
+        from misoclib.tools.litescope.host.driver.uart import LiteScopeUART2WishboneDriver
         port = args.port if not args.port.isdigit() else int(args.port)
-        wb = LiteScopeUARTDriver(port, args.baudrate, "./csr.csv", int(args.busword), debug=False)
+        wb = LiteScopeUART2WishboneDriver(port, args.baudrate, "./csr.csv", int(args.busword), debug=False)
     elif args.bridge == "etherbone":
         from misoclib.tools.litescope.host.driver.etherbone import LiteScopeEtherboneDriver
         wb = LiteScopeEtherboneDriver(args.ip_address, int(args.udp_port), "./csr.csv", int(args.busword), debug=False)

diff --git a/misoclib/tools/litescope/host/driver/uart.py b/misoclib/tools/litescope/host/driver/uart.py
index b1e42ead6188ff609f9e89b867f5752496d796e9..c4c90071c6dda2f59fa026b34d8ff06e13906fcf 100644 (file)
--- a/misoclib/tools/litescope/host/driver/uart.py
+++ b/misoclib/tools/litescope/host/driver/uart.py
@@ -7,7 +7,7 @@ def write_b(uart, data):
     uart.write(pack('B', data))
 
 
-class LiteScopeUARTDriver:
+class LiteScopeUART2WishboneDriver:
     cmds = {
         "write": 0x01,
         "read":  0x02
@@ -25,16 +25,8 @@ class LiteScopeUARTDriver:
         self.uart.close()
         self.uart.open()
         self.uart.flushInput()
-        try:
-            self.regs.uart2wb_sel.write(1)
-        except:
-            pass
 
     def close(self):
-        try:
-            self.regs.uart2wb_sel.write(0)
-        except:
-            pass
         self.uart.flushOutput()
         self.uart.close()