re PR target/63965 (ICE: in extract_constrain_insn, at recog.c:2230 on ppc64)

2014-11-21  Michael Meissner  <meissner@linux.vnet.ibm.com>

	PR target/63965
	* config/rs6000/rs6000.c (rs6000_setup_reg_addr_masks): Do not set
	Altivec & -16 mask if the type is not valid for Altivec registers.
	(rs6000_secondary_reload_memory): Add support for ((reg + const) +
	reg) that occurs during push_reload processing.

	* config/rs6000/altivec.md (altivec_mov<mode>): Add instruction
	alternative for moving constant vectors which are easy altivec
	constants to GPRs.  Set the length attribute each of the
	alternatives.

From-SVN: r217940

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 42a284b17810f0c4ec143f043b512895df7bbb37..9fb7f7a6ad8c62b29e9878e68243d210586b760d 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,16 @@
+2014-11-21  Michael Meissner  <meissner@linux.vnet.ibm.com>
+
+       PR target/63965
+       * config/rs6000/rs6000.c (rs6000_setup_reg_addr_masks): Do not set
+       Altivec & -16 mask if the type is not valid for Altivec registers.
+       (rs6000_secondary_reload_memory): Add support for ((reg + const) +
+       reg) that occurs during push_reload processing.
+
+       * config/rs6000/altivec.md (altivec_mov<mode>): Add instruction
+       alternative for moving constant vectors which are easy altivec
+       constants to GPRs.  Set the length attribute each of the
+       alternatives.
+
 2014-11-21  Matthew Fortune  <matthew.fortune@imgtec.com>
 
        * configure.ac: When checking for MIPS .module support ensure that

diff --git a/gcc/config/rs6000/rs6000-cpus.def b/gcc/config/rs6000/rs6000-cpus.def
index c1a7649c3fb3dcffe6bd48eba08dbe3f446a5246..7bd5891d13c7ac41ac49c74ee2ea68150238101a 100644 (file)
--- a/gcc/config/rs6000/rs6000-cpus.def
+++ b/gcc/config/rs6000/rs6000-cpus.def
@@ -38,14 +38,14 @@
 
   /* For ISA 2.06, don't add ISEL, since in general it isn't a win, but
      altivec is a win so enable it.  */
-  /* OPTION_MASK_VSX_TIMODE should be set, but disable it for now until
-     PR 58587 is fixed.  */
 #define ISA_2_6_MASKS_EMBEDDED (ISA_2_5_MASKS_EMBEDDED | OPTION_MASK_POPCNTD)
 #define ISA_2_6_MASKS_SERVER   (ISA_2_5_MASKS_SERVER                   \
                                 | OPTION_MASK_POPCNTD                  \
                                 | OPTION_MASK_ALTIVEC                  \
                                 | OPTION_MASK_VSX                      \
-                                | OPTION_MASK_UPPER_REGS_DF)
+                                | OPTION_MASK_UPPER_REGS_DF            \
+                                | OPTION_MASK_VSX_TIMODE)
+
 
 /* For now, don't provide an embedded version of ISA 2.07.  */
 #define ISA_2_7_MASKS_SERVER   (ISA_2_6_MASKS_SERVER                   \
@@ -188,7 +188,8 @@ RS6000_CPU ("power6x", PROCESSOR_POWER6, MASK_POWERPC64 | MASK_PPC_GPOPT
 RS6000_CPU ("power7", PROCESSOR_POWER7,   /* Don't add MASK_ISEL by default */
            POWERPC_7400_MASK | MASK_POWERPC64 | MASK_PPC_GPOPT | MASK_MFCRF
            | MASK_POPCNTB | MASK_FPRND | MASK_CMPB | MASK_DFP | MASK_POPCNTD
-           | MASK_VSX | MASK_RECIP_PRECISION | OPTION_MASK_UPPER_REGS_DF)
+           | MASK_VSX | MASK_RECIP_PRECISION | OPTION_MASK_UPPER_REGS_DF
+           | OPTION_MASK_VSX_TIMODE)
 RS6000_CPU ("power8", PROCESSOR_POWER8, MASK_POWERPC64 | ISA_2_7_MASKS_SERVER)
 RS6000_CPU ("powerpc", PROCESSOR_POWERPC, 0)
 RS6000_CPU ("powerpc64", PROCESSOR_POWERPC64, MASK_PPC_GFXOPT | MASK_POWERPC64)

diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c
index ea3e51120140c31c23e67d407e0dd1d59558c960..6d128c17408e6d013bcbc3a49c957a5886bab864 100644 (file)
--- a/gcc/config/rs6000/rs6000.c
+++ b/gcc/config/rs6000/rs6000.c
@@ -7730,13 +7730,6 @@ rs6000_legitimate_address_p (machine_mode mode, rtx x, bool reg_ok_strict)
       && legitimate_constant_pool_address_p (x, mode,
                                             reg_ok_strict || lra_in_progress))
     return 1;
-  /* For TImode, if we have load/store quad and TImode in VSX registers, only
-     allow register indirect addresses.  This will allow the values to go in
-     either GPRs or VSX registers without reloading.  The vector types would
-     tend to go into VSX registers, so we allow REG+REG, while TImode seems
-     somewhat split, in that some uses are GPR based, and some VSX based.  */
-  if (mode == TImode && TARGET_QUAD_MEMORY && TARGET_VSX_TIMODE)
-    return 0;
   /* If not REG_OK_STRICT (before reload) let pass any stack offset.  */
   if (! reg_ok_strict
       && reg_offset_p